Aerospace and Defense Products
Standard Featured Products
The ADIS16497 is a complete inertial system that includes a triaxis gyroscope and a triaxis accelerometer. Each inertial sensor in the ADIS16497 combines industry leading iMEMS® technology with signal conditioning that optimizes dynamic performance. The factory calibration characterizes each sensor for sensitivity, bias, alignment, and linear acceleration (gyroscope bias). As a result, each sensor has its own dynamic compensation formulas that provide accurate sensor measurements.
The ADIS16497 provides a simple, cost effective method for integrating accurate, multiaxis inertial sensing into industrial systems, especially when compared with the complexity and investment associated with discrete designs. All necessary motion testing and calibration are part of the production process at the factory, greatly reducing system integration time. Tight orthogonal alignment simplifies inertial frame alignment in navigation systems. The serial peripheral interface (SPI) and register structure provide a simple interface for data collection and configuration control.
The footprint and connector system of the ADIS16497 enable a simple upgrade from the ADIS16375, ADIS16480, ADIS16485, ADIS16488A, and ADIS16490. The ADIS16497 is available in an aluminum package that is approximately 47 mm × 44 mm × 14 mm and includes a standard connector interface.
- Precision instrumentation, stabilization
- Guidance, navigation, control
- Avionics, unmanned vehicles
- Precision autonomous machines, robotics
The ADIS16488 provides a simple, cost-effective method for integrating accurate, multiaxis inertial sensing into industrial systems, especially when compared with the complexity and investment associated with discrete designs. All necessary motion testing and calibration are part of the production process at the factory, greatly reducing system integration time. Tight orthogonal alignment simplifies inertial frame alignment in navigation systems. The SPI and register structure provide a simple interface for data collection and configuration control.
The ADIS16488 uses the same footprint and connector system as the ADIS16375, which greatly simplifies the upgrade process. It comes in a module that is approximately 47 mm × 44 mm × 14 mm and has a standard connector interface.
- Platform stabilization and control
- Personnel tracking
The ADIS16470 is a miniature MEMS inertial measurement unit (IMU) that includes a triaxial gyroscope and a triaxial accelerometer. Each inertial sensor in the ADIS16470 combines with signal conditioning that optimizes dynamic performance. The factory calibration characterizes each sensor for sensitivity, bias, alignment, linear acceleration (gyroscope bias), and point of percussion (accelerometer location). As a result, each sensor has dynamic compensation formulas that provide accurate sensor measurements over a broad set of conditions.
The ADIS16470 provides a simple, cost effective method for integrating accurate, multiaxis inertial sensing into industrial systems, especially when compared with the complexity and investment associated with discrete designs. All necessary motion testing and calibration are part of the production process at the factory, greatly reducing system integration time. Tight orthogonal alignment simplifies inertial frame alignment in navigation systems. The serial peripheral interface (SPI) and register structure provide a simple interface for data collection and configuration control.
The ADIS16470 is in a 44-ball, ball grid array (BGA) package that is approximately 11 mm × 15 mm × 11 mm.
- Navigation, stabilization, and instrumentation
- Unmanned and autonomous vehicles
- Smart agriculture/construction machinery
- Factory/industrial automation, robotics
- Virtual/augmented reality
- Internet of Moving Things
The AD9371 is a highly integrated, wideband RF transceiver offering dual channel transmitters and receivers, integrated synthesizers, and digital signal processing functions. The IC delivers a versatile combination of high performance and low power consumption required by 3G/4G micro and macro BTS equipment in both FDD and TDD applications. The AD9371 operates from 300 MHz to 6000 MHz, covering most of the licensed and unlicensed cellular bands. The IC supports receiver bandwidths up to 100 MHz. It also supports observation receiver and transmit synthesis bandwidths up to 250 MHz to accommodate digital correction algorithms.
The transceiver consists of wideband direct conversion signal paths with state-of-the-art noise figure and linearity. Each complete receiver and transmitter subsystem includes dc offset correction, quadrature error correction (QEC), and programmable digital filters, eliminating the need for these functions in the digital baseband. Several auxiliary functions such as an auxiliary analog- to-digital converter (ADC), auxiliary digital-to-analog converters (DACs), and general-purpose input/outputs (GPIOs) are integrated to provide additional monitoring and control capability.
An observation receiver channel with two inputs is included to monitor each transmitter output and implement interference mitigation and calibration applications. This channel also connects to three sniffer receiver inputs that can monitor radio activity in different bands.
The high speed JESD204B interface supports lane rates up to 6144 Mbps. Four lanes are dedicated to the transmitters and four lanes are dedicated to the receiver and observation receiver channels.
The fully integrated phase-locked loops (PLLs) provide high performance, low power fractional-N frequency synthesis for the transmitter, the receiver, the observation receiver, and the clock sections. Careful design and layout techniques provide the isolation demanded in high performance base station applications. All voltage controlled oscillator (VCO) and loop filter components are integrated to minimize the external component count.
A 1.3 V supply is required to power the core of the AD9371, and a standard 4-wire serial port controls it. Other voltage supplies provide proper digital interface levels and optimize transmitter and auxiliary converter performance. The AD9371 is packaged in a 12 mm × 12 mm, 196-ball chip scale ball grid array (CSP_BGA).
- 3G/4G micro and macro base stations (BTS)
- 3G/4G multicarrier picocells
- FDD and TDD active antenna systems
- Microwave, nonline of sight (NLOS) backhaul systems
RadioVerse: Concept to Creation at Lightspeed
The LTM4650 is a dual 25A or single 50A output switching mode step-down DC/DC μModule® (power module) regulator. Included in the package are the switching controllers, power FETs, inductors, and all supporting components. Operating from an input voltage range of 4.5V to 15V, the LTM4650 supports two outputs each with an output voltage range of 0.6V to 1.8V, each set by a single external resistor. Its high efficiency design delivers up to 25A continuous current for each output. Only a few input and output capacitors are needed. The LTM4650 is pin compatible with the LTM4620 (dual 13A, single 26A) and the LTM4630 (dual 18A, single 36A).
The device supports frequency synchronization, multiphase operation, Burst Mode operation and output voltage tracking for supply rail sequencing and has an onboard temperature diode for device temperature monitoring. High switching frequency and a current mode architecture enable a very fast transient response to line and load changes without sacrificing stability.
Fault protection features include overvoltage and overcurrent protection. The LTM4650 is offered in a 16mm × 16mm × 5.01mm BGA package.
|Vin Range||Vout Range||Comp||DC Vout Accy|
|LTM4650||4.5V to 15V||0.6V to 1.8V||Internal||1.5%|
|LTM4650-1B||4.5V to 15V||0.6V to 1.8V||External||1.5%|
|LTM4650-1A||4.5V to 15V||0.6V to 1.8V||External||0.8%|
|LTM4650A||4.5V to 16V||0.6V to 5.5V||Internal||1%|
|LTM4650A-1||4.5V to 16V||0.6V to 5.5V||External||1%|
- Processor, ASIC and FPGA Core Power
- Telecom and Networking Equipment
- Storage and ATCA Cards
- Industrial Equipment
The ADAR1000 is a 4-channel, X and Ku frequency band, beamforming core chip for phased arrays. This device operates in half-duplex between receive and transmit modes. In receive mode, input signals pass through four receive channels and are combined in a common RF_IO pin. In transmit mode, the RF_IO input signal is split and passes through the four transmit channels. In both modes, the ADAR1000 provides a ≥31 dB gain adjustment range and a full 360° phase adjustment range in the radio frequency (RF) path, with 6-bit resolution (less than ≤0.5 dB and 2.8°, respectively).
A simple 4-wire serial port interface (SPI) controls all of the on-chip registers. In addition, two address pins allow SPI control of up to four devices on the same serial lines. Dedicated transmit and receive load pins also provide synchronization of all core chips in the same array, and a single pin controls fast switching between the transmit and receive modes.
The ADAR1000 is available in a compact, 88-terminal, 7 mm × 7 mm, LGA package and is specified from −40°C to +85°C.
- Phased array radar
- Satellite communications systems
The ADRV9009 is a highly integrated, radio frequency (RF), agile transceiver offering dual transmitters and receivers, integrated synthesizers, and digital signal processing functions. The IC delivers a versatile combination of high performance and low power consumption demanded by 3G, 4G, and 5G macro cell time division duplex (TDD) base station applications.
The receive path consists of two independent, wide bandwidth, direct conversion receivers with state-of-the-art dynamic range. The device also supports a wide bandwidth, time shared observation path receiver (ORx) for use in TDD applications. The complete receive subsystem includes automatic and manual attenuation control, dc offset correction, quadrature error correction (QEC), and digital filtering, thus eliminating the need for these functions in the digital baseband. Several auxiliary functions, such as analog-to-digital converters (ADCs), digital-to-analog converters (DACs), and general-purpose inputs/outputs (GPIOs) for the power amplifier (PA), and RF front-end control are also integrated.
In addition to automatic gain control (AGC), the ADRV9009 also features flexible external gain control modes, allowing significant flexibility in setting system level gain dynamically.
The received signals are digitized with a set of four high dynamic range, continuous time Σ-Δ ADCs that provide inherent antialiasing. The combination of the direct conversion architecture, which does not suffer from out of band image mixing, and the lack of aliasing, relaxes the requirements of the RF filters when compared to traditional intermediate frequency (IF) receivers.
The transmitters use an innovative direct conversion modulator that achieves high modulation accuracy with exceptionally low noise.
The observation receiver path consists of a wide bandwidth, direct conversion receiver with state-of-the-art dynamic range.
The fully integrated phase-locked loop (PLL) provides high performance, low power, fractional-N RF frequency synthesis for the transmitter (Tx) and receiver (Rx) signal paths. An additional synthesizer generates the clocks needed for the converters, digital circuits, and the serial interface. A multichip synchronization mechanism synchronizes the phase of the RF local oscillator (LO) and baseband clocks between multiple ADRV9009 chips. Precautions are taken to provide the isolation required in high performance base station applications. All voltage controlled oscillators (VCOs) and loop filter components are integrated.
The high speed JESD204B interface supports up to 12.288 Gbps lane rates, resulting in two lanes per transmitter and a single lane per receiver in the widest bandwidth mode. The interface also supports interleaved mode for lower bandwidths, thus reducing the total number of high speed data interface lanes to one. Both fixed and floating point data formats are supported. The floating point format allows internal AGC to be invisible to the demodulator device.
The core of the ADRV9009 can be powered directly from 1.3 V regulators and 1.8 V regulators, and is controlled via a standard 4-wire serial port. Comprehensive power-down modes are included to minimize power consumption in normal use. The ADRV9009 is packaged in a 12 mm × 12 mm, 196-ball chip scale ball grid array (CSP_BGA).
- 3G, 4G, and 5G TDD macrocell base stations
- TDD active antenna systems
- Massive multiple input, multiple output (MIMO)
- Phased array radar
- Electronic warfare
- Military communications
- Portable test equipment
RadioVerse: Concept to Creation at Lightspeed
The AD9213 is a single 12-bit, 10.25 GSPS, RF analog-to-digital converter (ADC) with a 6.5 GHz input bandwidth. The AD9213 has been optimized to support high dynamic range frequency and time domain applications requiring wide instantaneous bandwidth and low code error rates (CER). The AD9213 features a 16-lane JESD204B interface to support its maximum bandwidth capability.
The AD9213 achieves industry leading dynamic range and linearity performance while consuming only 5 W. Based on an interleaved pipeline architecture, the AD9213 features a proprietary calibration and randomization technique that suppresses interleaving spurious artifacts into its noise floor. The excellent linearity performance of the AD9213 is preserved by a combination of on-chip dithering and calibration resulting in excellent spurious free performance over a wide range of input signal conditions.
Applications requiring less instantaneous bandwidth can benefit from the on-chip digital signal processing (DSP) capability of the AD9213 that reduces the output data rate along with the number of JESD204b lanes required to support it. The DSP path includes a digital downconverter (DDC) with a 48-bit, numerically controlled oscillator (NCO) followed by an I and Q digital decimator stage allowing for selectable decimation rates that are factors of two or three. For fast frequency hopping applications, the AD9213 NCO supports up to 16-profile settings with separate trigger input allowing for wide surveillance frequency coverage but at a reduced JESD204B lane count.
The AD9213 also supports sample accurate multichip synchronization that also includes synchronization of the NCOs. The AD9213 will be offered in a 192 flip-chip ball grid array (FcBGA) package. The AD9213 is specified over a junction temperature range of −10°C to +115°C.
The ADSP-SC57x/ADSP-2157x processors are members of the SHARC® family of products. The ADSP-SC57x processor is based on the SHARC+® dual-core and the ARM® Cortex®-A5 core. The ADSP-SC57x/ADSP-2157x SHARC processors are members of the single-instruction, multiple data (SIMD) SHARC family of digital signal processors (DSPs) that feature Analog Devices Super Harvard Architecture. These 32-bit/40-bit/64-bit floating-point processors are optimized for high performance audio/floating-point applications with large on-chip static random-access memory (SRAM), multiple internal buses that eliminate input/output (I/O) bottlenecks, and innovative digital audio interfaces (DAI). New additions to the SHARC+ core include cache enhancements and branch prediction, while maintaining instruction set compatibility to previous SHARC products.
By integrating a set of industry leading system peripherals and memory, the ARM Cortex-A5 and SHARC processor is the platform of choice for applications that require programmability similar to reduced instruction set computing (RISC), multimedia support, and leading edge signal processing in one integrated package. These applications span a wide array of markets, including automotive, professional audio, and industrial-based applications that require high floating-point performance.
The analog output ADXL356 and the digital output ADXL357 are low noise density, low 0 g offset drift, low power, 3-axis accelerometers with selectable measurement ranges. The ADXL356B supports the ±10 g and ±20 g ranges, the ADXL356C supports the ±10 g and ±40 g ranges, and the ADXL357 supports the ±10.24 g, ±20.48 g, and ±40.96 g ranges.
The ADXL356/ADXL357 offer industry leading noise, minimal offset drift over temperature, and long-term stability, enabling precision applications with minimal calibration.
The low drift, low noise, and low power ADXL357 enables accurate tilt measurement in an environment with high vibration, such as airborne IMUs. The low noise of the ADXL356 over higher frequencies is ideal for wireless condition monitoring.
The ADXL357 multifunction pin names may be referenced only by their relevant function for either the SPI or limited I2C interface.Applications
- Inertial measurement units (IMUs)/altitude and heading reference systems (AHRSs)
- Platform stabilization systems
- Structural health monitoring
- Seismic imaging
- Tilt sensing
- Condition monitoring