Five Output Ultralow Jitter Clock Distributor with PLL Provides Unique Multichip Output Synchronization Method

Jan 21 2015 - MILPITAS, CA
  • Linear Technology Corporation announces the LTC6950, a low phase noise integer-N synthesizer core with an ultralow jitter clock distribution output section. The LTC6950 is ideal for generating and distributing the low jitter signals essential to clocking data converters with a high signal-to-noise ratio (SNR). Maintaining low jitter on the data converter clock is fundamental to achieving outstanding SNR levels when digitizing or synthesizing high analog frequencies. For instance, modern electronic systems demand direct digitization of RF and high IF signals using an ADC. With 18fsRMS jitter (over the 12kHz to 20MHz bandwidth), the LTC6950 guarantees the best performance out of such a system.

    The LTC6950 incorporates Linear Technology’s proprietary EZSync output synchronization, a simple, effective method to edge-synchronize multiple outputs from either one chip or multiple chips. EZSync synchronization aligns the rising edges by simply asserting a common CMOS input with loose timing requirements. EZSync synchronization can also be used to produce repeatable and deterministic phase relationships between the clock divider outputs of devices that have this feature enabled.

    The phase-locked loop (PLL) inside the LTC6950 shines with a normalized in-band phase noise floor, or figure-of-merit, of –226dBc/Hz and exceptionally low –274dBc/Hz normalized 1/f phase noise which stays intact going through the clock distribution section. These specifications ensure designers take full advantage of the good phase noise performance of the external oscillator that is being locked by the LTC6950 and deliver the best jitter performance in this class of parts.

    To simplify the design process of the LTC6950, Linear Technology offers the ClockWizard free simulation and design tool. The ClockWizard GUI helps find loop filter component values with a click of a button, and accurately predicts the individual output’s phase noise and jitter, helping the designer make the correct choices during the design and debug phases. The ClockWizard simulation and design tool can be downloaded at

    The LTC6950 is specified over the full operating junction temperature range from –40°C to 105°C. It is available in a 5mm × 9mm, 48-lead plastic QFN package. The LTC6950 is priced at $9.95 each in 1,000-piece quantities and is available immediately from stock. Samples and demo boards may be requested by visiting or by contacting your local Linear Technology sales office.

    Summary of Features: LTC6950

    • Low Phase Noise & Jitter
    • Additive Jitter: 18fsRMS (12kHz to 20MHz)
    • Additive Jitter: 85fsRMS (10Hz to Nyquist)
    • EZSync Multichip Clock Edge Synchronization
    • Full PLL Core with Lock Indicator
    • –226dBc/Hz Normalized In-Band Phase Noise Floor
    • –274dBc/Hz Normalized 1/f Phase Noise
    • 1.4GHz Maximum VCO Input Frequency
    • Four Independent, Low Noise 1.4GHz LVPECL Outputs
    • One LVDS/CMOS Configurable Output
    • Five Independently Programmable Dividers Covering All Integers from 1 to 63
    • Five Independently Programmable VCO Clock Cycle Delays Covering All Integers from 0 to 63
    • –40°C to 105°C Operating Junction Temperature Range

    1.4GHz Clean Clocking Solution


    The USA list pricing shown is for budgetary use only. International prices may differ due to local duties, taxes, fees and exchange rates.

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