14-Bit 310Msps Dual ADC Family Enables Linearization of 60MHz Transmit Bandwidth Using Digital Predistortion

Oct 26 2011 - MILPITAS, CA
  • Linear Technology Corporation introduces a family of dual (LTC2158-14) and single (LTC2153-14) high IF sampling 14-bit, 310Msps analog-to-digital converters (ADCs) designed specifically for wide bandwidth digital predistortion (DPD) linearization applications. Digital predistortion is a closed-loop feedback system that samples the distortion bandwidth at the output of the base station transmitter and adjusts the input signal to cancel the power amplifier’s intermodulation distortion products. This enables the transmitter to operate at its highest efficiency, 1dB compression point, where the power amplifier (PA) response is nonlinear.

    Due to prior limitations in the performance of available ADCs, transmit bandwidths were limited to 20-40MHz, depending on whether an IF sampling or I/Q sampling DPD architecture was implemented. To linearize a transmit bandwidth of 20MHz, the feedback loop for the linearization algorithm must acquire fifth order intermodulation products out to 100MHz (five times the transmit bandwidth), requiring a 12-bit ADC with a minimum sample rate of 200Msps for IF sampling, or 100Msps for I/Q sampling. Due to increasing data demands from mobile users, next-generation base stations are being architected to achieve much higher transmit bandwidths of up to 60MHz. To linearize a 60MHz transmit bandwidth requires an ADC with a minimum resolution of 14-bits and an I/Q sampling architecture with a minimum sample rate of 300Msps. In addition, the closed loop DPD algorithm requires short latency in the feedback path to achieve better efficiency in the PA.

    The LTC2158-14 is the first dual, 310Msps ADC on the market to enable linearization of transmission bandwidths up to 60MHz using I/Q sampling, and offers a short pipeline latency of just 5 clock cycles for fast adaptation. The single version, LTC2153-14, is ideal for IF sampling architectures with transmit bandwidths of up to 30MHz.

    Operating from a single 1.8V supply, the dual LTC2158-14 consumes 362mW/channel at 310Msps and offers signal to noise ratio (SNR) performance of 68.8dB and SFDR of 88dB at baseband with an easy-to-drive 1.32VP-P input range. The LTC2158 and LTC2153 are part of a pin-compatible family of 170Msps to 310Msps dual and single ADCs, offered in 14-bit and 12-bit resolutions. Analog full power bandwidth of 1.25GHz and ultralow jitter of 0.15psRMS enables undersampling of IF frequencies with excellent noise performance. The ADCs offer double data rate (DDR) LVDS digital outputs as well as programmable LVDS output current and optional 100Ω termination.

    Available in compact 9mm × 9mm (dual) and 6mm × 6mm (single) QFN packages, the ADCs may be ordered in commercial or industrial temperature grades. Demonstration boards and samples are immediately available through your local Linear Technology sales office. The 14-bit dual 310Msps LTC2158-14 is priced at $168.30 each in 1,000-piece quantities. The complete product family can be found at: www.linear.com/hsadc.

    Summary of Features: LTC2153/LTC2158

    • 14-bit/12-Bit, 310Msps Single/Dual ADCs
    • 68.8dB SNR, 88dB SFDR (14-bits)
    • 724mW (362mW per channel)
    • 1.8V Single Supply Operation
    • DDR LVDS Outputs
    • Easy-to-Drive 1.32VP-P Input Range
    • 1.25GHz Full Power Bandwidth S/H
    • Optional Clock Duty Cycle Stabilizer
    • Low Power Sleep & Nap Modes
    • Serial SPI Port for Configuration
    • Easy Evaluation Using PScope Analysis Software

    LTC2158-14 I/Q DPD Receiver


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