1. Data Sheet Errata

Documentation Errata for ADSP-BF512/ADSP-BF514/ADSP-BF514F16/ADSP-BF516/ADSP-BF518/ADSP-BF518F16 Blackfin Embedded Processor Data Sheet

Chapter: / Page 6

Doc ID: DOC-1543


The block diagram in Figure 4 contains the following errors:

  • CE should be CS.
  • RST should be HOLD.
  • WP is missing. It should appear under RST as a no connect (NC).

Chapter: / Page 30

Doc ID: DOC-1544


The description of the timing requirement for tRST_IN_PWR is missing VDDFLASH. The correct timing requirement is as follows:

RESET Deasserted after the VDDINT, VDDEXT, VDDRTC, VDDMEM, VDDOTP, VDDFLASH, and CLKIN Pins are Stable and Within Specification.

Last Update Date: 2017-05-08