Application Note 304 provides a logical diagram of the interface of the Dallas Semiconductor/Maxim DS2151 T1 single chip transceiver (SCT) and DS2153 E1 SCT to the AT&T T7270.
- CMS = 0 in the T7270.
- Gate #1 is used to condition the frame sync to meet the timing requirements of the T7270.
- In the master, no elastic stores are enabled; in the slave, both the receive and the transmit side elastic stores are enabled.
- A "loop-timed" application is shown.
- In the master, RCHBLK is programmed to go high during the last channel.
- Timing is shown below: