工具、软件和仿真模型

工具、软件和仿真模型 — AD9516-3 : 14路输出时钟发生器,集成2.0 GHz VCO

 
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ADIsim Design/Simulation Tools (1)
  • ADIsimCLK™设计与评估软件
    ADIsimCLK is the design tool developed specifically for Analog Devices' range of ultra-low jitter clock distribution and clock generation products. Whether your application is in wireless infrastructure, instrumentation, networking, broadband, ATE or other areas demanding predictable clock performance, ADIsimCLK will enable you to rapidly develop, evaluate and optimize your design.
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