TIGERSHARC PROCESSOR ROADMAP

New generations of TigerSHARC® Processors are currently in development that will continue to offer higher levels of performance density. The key to increasing performance density is maintaining a balance between greater computational performance, larger amounts of on chip memory integration, and greater I/O bandwidth. Improvements such as increased processor clock rates, architectural enhancements, utilization of new memory technologies, and higher bandwidth I/O interfaces will enable TigerSHARC-based designs to increase system level performance while reducing costs, power consumption, and size.

By basing designs on a TigerSHARC programmable processor, applications in wireless communications, military, industrial, imaging, and medical markets will be able to leverage IP reuse from generation to generation reducing R&D costs and time to market. The newest entries into the TigerSHARC family, the ADSP-TS201S, ADSP-TS202S, and ADSP-TS203S, offer new levels of performance density with 4800 MMACs of 16-bit performance, 3600 MFLOPS of floating-point performance, 24 Mbits of on- chip memory, and 5 Gbytes of I/O bandwidth.

TigerSHARC Processors will continue to be designed with the goal of offering the industry's best performance density while maintaining code compatibility so that new generations of multiprocessing systems can be designed to meet the ever more demanding system cost, power, and size requirements of the future.

Click to Enlarge

SHARC/TigerSHARC Roadmap

For a detailed roadmap, please contact an ADI sales representative.

沪ICP备09046653号
提供意见反馈 X
content here.
content here.

提供意见反馈

关闭