新闻
- 2009年02月24日 ADI 公司推出更简化的时钟发生器架构
- 2008年10月06日 ADI公司的可编程时钟发生器简化系统设计并减少时钟器件数量
新产品
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AD9571- Ethernet Clock Generator, 10 Clock Outputs
The AD9571 provides a multioutput clock generator function comprising a dedicated PLL core that is optimized for Ethernet line card applications. The integer-N PLL design is based on the Analog Devices, Inc., proven portfolio of high performance, low jitter frequency synthesizers to maximize network performance. Other applications with demanding phase noise and jitter requirements also benefit More
中文产品数据手册 Rev 0, 09/2009 (pdf 360kB)
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AD9572- Fiber Channel/Ethernet Clock Generator IC, PLL Core, Dividers, 7 Clock Outputs
The AD9572 provides a multioutput clock generator function along with two on-chip PLL cores, optimized for fiber channel line card applications that include an Ethernet interface. The integer-N PLL design is based on the Analog Devices, Inc., proven portfolio of high performance, low jitter frequencysynthesizers to maximize network performance. Other applications with demanding phase noise and More
中文产品数据手册 Rev 0, 08/2009 (pdf 415kB)
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ADCLK948- Two Selectable Inputs, 8 LVPECL Outputs SiGe Clock Fanout Buffer
The ADCLK948 is an ultrafast clock fanout buffer fabricated on the Analog Devices, Inc., proprietary XFCB3 silicon german-ium (SiGe) bipolar process. This device is designed for high speed applications requiring low jitter.
The device has two selectable differential inputs via the IN_SEL control pin. Both inputs are equipped with center tapped, differential, 100 Ω on-chip termination More
中文产品数据手册 Rev 0, 07/2009 (pdf 709kB)
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AD9547- 双路/四路输入网络时钟发生器/同步器
AD9547针对许多系统提供同步功能，包括同步光纤网络(SONET/SDH)。该器件产生的输出时钟可以与两路差分或四路单端外部输入参考时钟之一同步。数字锁相环(PLL)可以降低与外部参考时钟相关的输入时间抖动或相位噪声。借助数字控制环路和保持电路，即使所有参考时钟都失效，AD9547也能连续产生干净（低抖动）、有效的输出时钟。
AD9547的工作温度范围为−40°C至+85°C工业温度范围。
应用- 网络同步
- 清除参考时钟抖动
- 最高达到OC-192的SONET/SDH时钟，包括FEC
- Stratum 2保持、抖动清除及相位瞬态控制
- Stratum 3E和Stratum 3参考时钟
- 无线基站、控制器
- 电缆基础设施
- 数据 More
中文产品数据手册 Rev 0, 08/2009 (pdf 1753kB)
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