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    <title>New Products for 时钟分配 | Analog Devices</title>
    <link>http://www.analog.com</link>
    <description>New Products for 时钟分配 | Analog Devices</description>
    <pubDate>Tue, 22 Sep 2009 04:00:00 GMT</pubDate>
    <dc:date>2009-09-22T04:00:00Z</dc:date>
    <item>
      <title>AD9571, Ethernet Clock Generator, 10 Clock Outputs</title>
      <link>http://www.analog.com/zh/clock-and-timing/clock-generation-and-distribution/ad9571/products/product.html</link>
      <description>The AD9571 provides a multioutput clock generator function comprising a dedicated PLL core that is optimized for Ethernet line card applications. The integer-N PLL design is based on the Analog Devices, Inc., proven portfolio of high performance, low jitter frequency synthesizers to maximize network performance. Other applications with demanding phase noise and jitter requirements also benefit</description>
      <category>时钟分配</category>
      <category>时钟分配</category>
      <pubDate>Tue, 22 Sep 2009 04:00:00 GMT</pubDate>
      <guid>http://www.analog.com/zh/clock-and-timing/clock-generation-and-distribution/ad9571/products/product.html</guid>
      <dc:date>2009-09-22T04:00:00Z</dc:date>
    </item>
    <item>
      <title>AD9572, Fiber Channel/Ethernet Clock Generator IC, PLL Core, Dividers, 7 Clock Outputs</title>
      <link>http://www.analog.com/zh/clock-and-timing/clock-generation-and-distribution/ad9572/products/product.html</link>
      <description>The AD9572 provides a multioutput clock generator function along with two on-chip PLL cores, optimized for fiber channel line card applications that include an Ethernet interface. The integer-N PLL design is based on the Analog Devices, Inc., proven portfolio of high performance, low jitter frequencysynthesizers to maximize network performance. Other applications with demanding phase noise and</description>
      <category>时钟分配</category>
      <category>时钟分配</category>
      <pubDate>Fri, 14 Aug 2009 14:27:35 GMT</pubDate>
      <guid>http://www.analog.com/zh/clock-and-timing/clock-generation-and-distribution/ad9572/products/product.html</guid>
      <dc:date>2009-08-14T14:27:35Z</dc:date>
    </item>
    <item>
      <title>ADCLK948, Two Selectable Inputs, 8 LVPECL Outputs SiGe Clock Fanout Buffer</title>
      <link>http://www.analog.com/zh/clock-and-timing/clock-generation-and-distribution/adclk948/products/product.html</link>
      <description>The ADCLK948 is an ultrafast clock fanout buffer fabricated on the Analog Devices, Inc., proprietary XFCB3 silicon german-ium (SiGe) bipolar process. This device is designed for high speed applications requiring low jitter.&lt;/p&gt;&lt;p&gt;
The device has two selectable differential inputs via the IN_SEL control pin. Both inputs are equipped with center tapped, differential, 100 Ω on-chip termination</description>
      <category>时钟分配</category>
      <category>时钟分配</category>
      <pubDate>Thu, 06 Aug 2009 09:07:06 GMT</pubDate>
      <guid>http://www.analog.com/zh/clock-and-timing/clock-generation-and-distribution/adclk948/products/product.html</guid>
      <dc:date>2009-08-06T09:07:06Z</dc:date>
    </item>
    <item>
      <title>AD9547, 双路/四路输入网络时钟发生器/同步器</title>
      <link>http://www.analog.com/zh/clock-and-timing/clock-generation-and-distribution/ad9547/products/product.html</link>
      <description>AD9547针对许多系统提供同步功能，包括同步光纤网络(SONET/SDH)。该器件产生的输出时钟可以与两路差分或四路单端外部输入参考时钟之一同步。数字锁相环(PLL)可以降低与外部参考时钟相关的输入时间抖动或相位噪声。借助数字控制环路和保持电路，即使所有参考时钟都失效，AD9547也能连续产生干净（低抖动）、有效的输出时钟。&lt;/p&gt;&lt;p&gt;
AD9547的工作温度范围为−40°C至+85°C工业温度范围。&lt;/p&gt;&lt;br&gt;
&lt;b&gt;应用&lt;/b&gt;
&lt;li&gt;网络同步&lt;/li&gt;
&lt;li&gt;清除参考时钟抖动&lt;/li&gt;
&lt;li&gt;最高达到OC-192的SONET/SDH时钟，包括FEC&lt;/li&gt;
&lt;li&gt;Stratum 2保持、抖动清除及相位瞬态控制&lt;/li&gt;
&lt;li&gt;Stratum 3E和Stratum 3参考时钟&lt;/li&gt;
&lt;li&gt;无线基站、控制器&lt;/li&gt;
&lt;li&gt;电缆基础设施&lt;/li&gt;
&lt;li&gt;数据</description>
      <category>时钟分配</category>
      <category>时钟分配</category>
      <pubDate>Tue, 04 Aug 2009 07:56:13 GMT</pubDate>
      <guid>http://www.analog.com/zh/clock-and-timing/clock-generation-and-distribution/ad9547/products/product.html</guid>
      <dc:date>2009-08-04T07:56:13Z</dc:date>
    </item>
    <item>
      <title>AD9552, 振荡器频率上变频器</title>
      <link>http://www.analog.com/zh/clock-and-timing/clock-generation-and-distribution/ad9552/products/product.html</link>
      <description>AD9552是一款小数N分频、基于锁相环(PLL)的时钟发生器，专为取代高频晶体振荡器和谐振器而设计。该器件采用Σ-Δ调制器(SDM)来处理小数频率合成。用户将单端时钟信号直接与REF引脚相连，或者在XTAL引脚上连接一个晶体谐振器，即可提供输入参考信号。&lt;/p&gt;

&lt;p&gt;AD9552为引脚可编程器件，根据8种常用输入频率的其中一种频率，可提供64种标准输出频率中的一种频率。该器件还有一个三线式SPI接口，用户可以通过该接口自定义设置输入与输出频率比。&lt;/p&gt;

&lt;p&gt;AD9552需用外部电容来构成PLL的环路滤波器。虽然AD9552严格按照CMOS工艺制造，但其输出与LVPECL、LVDS或单端CMOS逻辑电平兼容。&lt;/p&gt;

&lt;p&gt;额定工作温度范围为−40°C至+85°C工业温度范围。&lt;/p&gt;

&lt;p class="padding"&gt;&lt;strong&gt;应用&lt;/strong&gt;&lt;/p&gt;
&lt;u</description>
      <category>时钟分配</category>
      <category>时钟分配</category>
      <pubDate>Tue, 28 Jul 2009 15:03:03 GMT</pubDate>
      <guid>http://www.analog.com/zh/clock-and-timing/clock-generation-and-distribution/ad9552/products/product.html</guid>
      <dc:date>2009-07-28T15:03:03Z</dc:date>
    </item>
    <item>
      <title>AD9573, PCI-Express Clock Generator IC, PLL Core, Dividers, Two Outputs</title>
      <link>http://www.analog.com/zh/clock-and-timing/clock-generation-and-distribution/ad9573/products/product.html</link>
      <description>The AD9573 provides a highly integrated, dual output clock generator function including an on-chip PLL core that is optimized for PCI-e applications. The integer-N PLL design is based on the Analog Devices, Inc., proven portfolio of high performance, low jitter frequency synthesizers to maximize line card performance. Other applications with demanding phase noise and jitter requirements also</description>
      <category>时钟分配</category>
      <category>时钟分配</category>
      <pubDate>Thu, 23 Jul 2009 13:32:29 GMT</pubDate>
      <guid>http://www.analog.com/zh/clock-and-timing/clock-generation-and-distribution/ad9573/products/product.html</guid>
      <dc:date>2009-07-23T13:32:29Z</dc:date>
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