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Volume 9, Issue 5 | YOUR SEMICONDUCTOR SOLUTIONS RESOURCE |
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C o n t e n t s Ultrabroadband PLL >> Integrated IF Quadrature Modulator >> New Broadband Demodulator IC Offers Excellent Dynamic Range >> High Linearity Mixers Enable Designs with Low Noise Requirements >> RF/IF SOT-89 Gain Blocks Offer Highest Dynamic Range >> 1 W Broadband RF Driver Amplifier Consumes Less Power >> RMS Power Detector Offers Unparalleled Performance >> Reference Design for Femtocell Networks >> Transceiver Enables Pico- and Microcell Base Stations >> New TxDAC Makes Direct RF Signals Possible >> Dual High Speed ADC Reduces Power >> Clock IC Generates Up to 400 MHz >> Design RF Systems in Less Time with Free Tools >> Sub-1 GHz Transceivers Deliver Robust RF Performance >>
All prices in this bulletin are in USD in quantities greater than 1000 (unless otherwise noted), recommended lowest grade resale, FOB U.S.A.
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Clock IC Generates Up to 400 MHz from 1 PPS GPS Signal
The AD9548 is the first clock chip in the industry to directly generate up to a 400 MHz output clock, with extremely low phase noise, that is locked to a standard one pulse-per-second (PPS) GPS clock signal. This performance is a result of combining Analog Devices' proprietary direct digital synthesis (DDS) technology with a state-of-the-art digital phase-locked loop (DPLL). Other solutions for synchronizing to the GPS 1 PPS source typically rely on one or more frequency upconversion steps. Maintaining low output noise, while providing over eight orders of magnitude of frequency scaling (1 Hz input to over 100 MHz output), is a significant challenge. The AD9548 is able to mitigate this effect thanks to a digital loop filter capable of bandwidths as low as 1 MHz (10 Hz to 3 Hz). By incorporating Analog Devices' ADCLK buffer series along with the AD9548 in a design, up to 16 GPS-synchronized output signals can be realized, enough to provide the timing reference for very complex systems.
The fanout buffers ADCLK946/ADCLK954 and ADCLK846/ADCLK854 provide between 6 and 24 copies of the input. These devices yield very low additive jitter from 60 fs to 150 fs and low clock output skew, making them ideal for general-purpose clock distribution. The outputs of the ADCLK8xx buffer family can be set to LVDS or CMOS logic levels, while outputs of the ADCLK9xx family can be set to LVPECL or ECL logic levels. The ADIsimCLK™ design and simulation tool is available to clock and timing engineers in order to develop fast-to-market applications. It can be downloaded for free at www.analog.com/ADIsimCLK.
Design RF Systems in Less Time with Free Tool Downloads Analog Devices supports its broad RF-IC portfolio with a comprehensive suite of design tools. RF systems design is an extremely complex and time-consuming process, and these tools reduce design risk and time-to-market by making the overall RF-to-digital design practice simpler, faster, more accurate, and more robust. Download these free tools now at www.analog.com/rftools.
ADIsimRF ADIsimPLL ADIsimSRD Design Studio
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