The AD9789 TxDAC+ transmit DAC with 4-channel signal processing answers this challenge with an effective symbols-to-RF architecture that enables a lower cost FPGA than traditional cable modem termination systems (CMTS). The AD9789 is a flexible QAM encoder/interpolator/upconverter combined with a high performance 2400 MSPS 14-bit DAC core on a single chip. Its flexible digital interface can accept up to four channels of complex data. The QAM encoder supports constellation sizes of 16, 32, 64, 128, and 256 with SRRC filter coefficients for all standards. The on-chip rate converter allows a wide range of baud rates to be supported without sacrificing the advantage of a fixed DAC clock rate. The digital upconverter can place up to four channels from 0 to 0.5 × f_DAC. This permits four contiguous DOCSIS channels to be synthesized and placed anywhere in the DOCSIS band. The AD9789 includes a serial peripheral interface (SPI) for device configuration and status register readback. The flexible digital interface is pin-configurable to operate in CMOS or LVDS mode and can be configured for data bus widths from 4 bits to 32 bits and can accept real or complex data. The QAM encoder and SRRC filter may be bypassed to enable this DAC to be used in other applications such as wireless infrastructure. The nominal DAC output current is 20 mA, which produces a peak 0 dBm of power into a 50 Ω load.

The AD9789 operates from 1.5 V, 1.8 V, and 3.3 V supplies and dissipates a total power consumption of 1.7 W while operating at maximum speed. It is supplied in a 164-lead chip-scale BGA for lower thermal impedance and reduced package parasitics. For optimal performance of the AD9789, the ADCLK914 high voltage differential signaling (HVDS) clock driver should be used. HVDS logic produces a very large output differential swing of 3.8 V—making it ideal for applications requiring a high slew rate and low noise. The ADCLK914 operates up to 7.5 GHz with a 160 ps propagation delay and adds only 110 fs random jitter.