C o n t e n t s

ADC with Configurable Filtering Adds Flexibility >>

High Speed ADC Portfolio Responds to Market Demands >>

High Performance ADC Dissipates Only 15 mW to Solve Heat Dissipation >>

Smallest SAR ADC Targets Space-Constrained Applications >>

ADC Selection Guide >>

ADC Selection Guide, continued >>

ADC with Integrated Quadrature Error Correction Minimizes Errors >>

Why Use an ADC Driver Amplifier? >>

Circuits from the Lab—Tested Design Resource >>

Buffer Enhances Clock Integrity to Enable Rated Performance from High Performance >>

Diff Amp Calculator Design Tool >>

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Circuits from the LabCircuits from the Lab—Tested Design Resource Provides Faster Time to Market and Lowers Risks

As design engineers look to build systems from the ground up, they often rely on various calculators, simulation models, software, and other design tools to aid in the selection, evaluation, and implementation of components.

Circuits from the Lab™ by Analog Devices is a new design assistance resource that provides design engineers with tested circuit solutions for many common applications. Circuits from the Lab pairs at least two complementary components, such as an ADC and amplifier, to present a circuit optimized for a targeted application. Each circuit has been built and tested in the lab and can be easily integrated into designs, resulting in reduced design risk and faster time to market.

Featured Circuits from the Lab

CN-0041 Circuit Note, Single-Ended-to-Differential Conversion Using the AD8138 Low Distortion Differential ADC Driver and AD7356 5 MSPS, 12-Bit SAR ADC

This circuit provides single-ended-to-differential conversion of an input signal to the AD7356, 5 MSPS, 12-bit SAR ADC. This circuit has been designed to ensure maximum performance of the AD7356 by providing adequate settling time and low impedance. An ideal method of applying differential drive to the AD7356 is to use a differential amplifier, such as the AD8138. This part can be used as a single-ended-to-differential amplifier or as a differential-to-differential amplifier. The AD8138 also provides common-mode level shifting. For access to this circuit note, visit www.analog.com/CN-0041.

AD8138 AD7356


Buffer Enhances Clock Integrity to Enable Rated Performance from High Performance, High Speed ADCs

Designers using high performance, high speed analog-to-digital converters (ADC) in their systems do so to bring speed, accuracy, and high resolution to their system. One of the primary selection criteria for the ADC is its signal-to-noise (SNR) ratio. Ancillary design elements impact the converter's performance—and a key consideration is clock integrity. Jitter on the input clock of the ADC will degrade its SNR performance, and it can be a significant challenge to maintain a good low noise/low jitter clock signal throughout the entirety of the system's clock tree.

Analog Devices has developed a broad portfolio of clock buffers designed to help designers solve this clock integrity challenge. With a clock buffer inserted between the converter and the system clock tree, jitter figures on the order of 75 fs for LVPECL fanout buffers and extremely low skew on the order of 9 ps (picoseconds) can readily be achieved. These buffer ICs also provide up to 12 channels of low jitter clock fanout and sharpen the edge of a clock signal that may have been slowed by long trace routing across the PCB.

The ideal clock signal for a data converter features not only low phase noise/jitter but also very sharp rise and fall edges. When a very sharp edge for just one or two converters is needed, the ADCLK905, ADCLK907, ADCLK914, and ADCLK925 clock buffers can provide very fast edges with extremely little impact on the noise of the clock signal when located in close proximity to the converter. In addition to sharpening edges, parts such as the ADCLK914 also provide high differential voltage swing, which can serve to limit ADC coupling noise.

ADI has a portfolio of low jitter clock buffer products ranging from one to 12 outputs and various logic families to meet the requirements of clocking high performance, high speed ADCs.


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