C o n t e n t s

ADC with Configurable Filtering Adds Flexibility >>

High Speed ADC Portfolio Responds to Market Demands >>

High Performance ADC Dissipates Only 15 mW to Solve Heat Dissipation >>

Smallest SAR ADC Targets Space-Constrained Applications >>

ADC Selection Guide >>

ADC Selection Guide, continued >>

ADC with Integrated Quadrature Error Correction Minimizes Errors >>

Why Use an ADC Driver Amplifier? >>

Circuits from the Lab—Tested Design Resource >>

Buffer Enhances Clock Integrity to Enable Rated Performance from High Performance >>

Diff Amp Calculator Design Tool >>

All prices in this bulletin are in USD in quantities greater than 1000 (unless otherwise noted), recommended lowest grade resale, FOB U.S.A.

YOUR SEMICONDUCTOR SOLUTIONS RESOURCEVolume 10, Issue 2

ANALOG-TO-DIGITAL
CONVERTER AND DRIVER ICs

New High Speed ADC Portfolio Responds to Today's Market Demands for LowerPower and Smaller Package Footprint

Industries such as test instrumentation, communications, and healthcare have traditionally provided a large market for state-of-the-art, high speed, high performance ADCs. These markets were early adopters of the latest breakthrough technology, which they in turn used to enable the next generation of their products and systems. The converter requirements of these markets were typically driven by signal chain performance specifications rather than power dissipation and package size. However, today's market environment emphasizes reducing overall system power ("going green") to enable lower total cost of ownership for operators and to address the global mandate for energy conservation. In addition, there is a trend to make systems portable and battery-operated, which puts further constraints on board space and cooling capacities. These market pressures are, of course, to be met with no reduction in system performance. A new breed of high speed converter is needed.

Solution
In response to these market demands for low power consumption and smaller package sizes in high speed, high performance ADCs with no corresponding trade-offs in performance, ADI has developed a family of 26 new 10-bit to 16-bit ADCs that move the power curve decidedly downward. In fact, in the case of the 16-bit, 125 MSPS ADCs, power is reduced by 87% over competing devices. This lower power and its accompanying reduced heat dissipation requirement have enabled the use of smaller, pin-compatible package sizes to reduce board space and offer flexibility in system upgrade options.
AD9269 AD9265 AD9266 AD9649

AD9269

Industry's Smallest 16-Bit, Low Power, Single Channel ADC Spans 20 MSPS to 80 MSPS

The AD9266 single channel, 16-bit, low power ADC is available in a small 5 mm × 5 mm package, and the pinout supports resolutions from 10 bits to 16 bits. The low power multistage ADC core is based on a proprietary, high performance, sample-and-hold circuit and on-chip voltage reference. The product uses a differential pipeline architecture with output error correction logic to provide 16-bit accuracy at 80 MSPS data rates and guarantees no missing codes over the full operating temperature range. The ADC contains several features designed to maximize flexibility and minimize system cost, such as programmable clock and data alignment and programmable digital test pattern generation. The available digital test patterns include built-in deterministic and pseudorandom patterns, along with custom user-defined test patterns entered via the SPI.

Industry's First Low Power, Single Channel, 16-Bit ADC Clocks at 125 MSPS

The AD9265 single channel, 16-bit, low power ADC was designed to support communications applications requiring low bill of material costs, small size, and flexibility. Consuming only 370 mW, this breakthrough in power consumption represents a 51% savings compared to competitive low power solutions. The ADC core features a multistage, differential pipelined architecture with integrated output error correction logic. The AD9265 features a wide bandwidth differential sample-and-hold analog input amplifier supporting a variety of user-selectable input ranges. An integrated voltage reference eases design considerations. A duty cycle stabilizer provides means to compensate for variations in the ADC clock duty cycle, allowing the converters to maintain excellent performance. The ADC output data are either parallel 1.8 V CMOS or 1.8 V LVDS (DDR). Flexible power-down options allow significant power savings when desired. Programming for setup and control are accomplished using a 3-bit SPI-compatible serial interface. Production quantities are available now.

Industry First: Sub 100 mW/Channel, Low Power, Dual Channel ADC Spans 20 MSPS to 80 MSPS

The AD9269 dual channel, 16-bit, low power ADC consumes 93 mW per channel, which is 6.5 times lower than competing devices. The AD9269 is a monolithic, dual channel, 16-bit, 20 MSPS/40 MSPS/65 MSPS/80 MSPS ADC featuring a high performance sampleand- hold circuit and on-chip voltage reference. It's also the industry's first 16-bit ADC family to include a QEC and dc offset digital processing block. This converter uses multistage differential pipeline architecture with output error correction logic to provide 16-bit accuracy at 80 MSPS data rates, and guarantees no missing codes over the full operating temperature range. The ADC operates from a 1.8 V supply and contains several features designed to maximize flexibility and minimize system cost, such as programmable clock and data alignment and programmable digital test pattern generation.

The entire high speed, low power ADC portfolio is included in the selection table on Page 4 and Page 5 of this solutions bulletin.

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