Σ-Δ ADCs have long been the architecture of choice for applications requiring both high resolution and high accuracy. The standard product implementation of this converter architecture has been within a discrete time domain and limited to a few MHz of bandwidth. However, the CTSD can provide the advantages of its discrete time counterpart, in addition to a wider bandwidth, inherent antialiasing, and an easy to drive input structure.

A key benefit of the CTSD architecture, utilized in the AD926x family of converters from ADI, is the inherent alias immunity that it offers. Since the sampling operation of a CTSD-based ADC occurs at the output of the internal loop filter, which is the same point where quantization noise is injected into the loop, aliases are attenuated by a similar mechanism, which attenuates quantization noise. This process, coupled with a 640 MSPS high speed modulator and a 32× oversampling ratio (OSR) for a 10 MHz input signal, ultimately eliminates the need for antialiasing filters. In addition, the continuous time loop filter architecture enables a passive 1 kΩ input impedance and results in a –3 dBm input power requirement for a 2 V p-p input voltage swing that significantly relaxes the requirements of the ADC driver amplifier. This feature contrasts with a typical switched capacitor input structure that represents a significant challenge to filter and drive.

Click here to view full size image

The AD926x CTSD ADCs achieve a high dynamic range of 86 dB, and an SNR of 84.5 dBFS up to a 10 MHz analog input bandwidth. The ADC provides an extremely low 15 dB noise figure, which is nearly a 7 dB improvement over current, state-of-the-art wideband converters. The low noise figure reduces the front-end gain, thereby relaxing linearity requirements in an RF system. In addition, the high dynamic range makes it possible to eliminate the automatic gain control commonly employed in many communication systems.

In emerging applications, such as wireless communications, medical imaging, and radar systems, accurate and high speed signal conversion are key requirements. The high SNR and wide bandwidth, in addition to the reduction in requirements of system level components, make CTSD-based ADCs an ideal fit for these applications. An example of this is illustrated by using the AD9262 in combination with ADI's high performance ADL5382 quadrature demodulator and AD9520 clock generation and distribution products to implement a 20 MHz BW high performance and low part count 700 MHz to 2.7 GHz direct conversion receiver.

4.8 kHz, Ultralow Noise, 24-BitΣ-Δ ADC with PGA Enables Faster Precision Measurement

Today's designs demand more speed from Σ-Δ ADCs as the market requires boosted throughput or a greater number of sensor channels that must be processed in the same amount of time. In addition, the resolution or dc accuracy must not be compromised.

The new AD7190 Σ-Δ ADC features an advanced on-chip PGA with ultralow noise and drift from dc to 4.8 kHz. The innovative design of the integrated PGA allows the AD7190 to realize an ultralow noise of only 8.5 nV rms at a 4.7 Hz data rate with a gain setting of 128, translating to 20.5 bits of noise-free resolution on an input signal of only ±40 mV. However, unlike other devices on the market, the AD7190 is able to extend this performance into higher speeds. It is the first Σ-Δ ADC to achieve greater than 16-bit noise-free resolution on a ±40 mV input signal beyond 1 kHz data rates. In addition, the AD7190 achieves 16 bits of noise-free resolution at a data rate of 2.4 kHz. Delivering superior noise-free resolution across the widest data rate and input signal range of any Σ-Δ ADC, the AD7190 offers designers the flexibility to use a single data converter solution in multiple lines of end equipment. For more information on Σ-Δ converters, visit www.analog.com/sigmadelta.

Click here to view full size image

Back to top