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News on ICs
for the entire RF signal chain
New RF ICs:
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| These products
are in full production and available for sampling/ordering
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| 18 GHz Microwave PLL Synthesizer |
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Integrated SiGe prescaler |
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Software compatible with the ADF4106/ADF4107/ADF4108 family of PLLs |
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2.85 V to 3.15 V PLL power supply |
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Programmable charge pump currents |
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Programmable dual-modulus prescaler 8/9, 16/17, 32/33, 64/65 |
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3-wire serial interface |
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Analog and digital lock detect |
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Hardware and software power-down mode |
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Learn more and order sample of the ADF41020 PLL Synthesizer
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| Dual-channel 14-Bit, 250 MSPS/170 MSPS, 1.8 V Analog-to-Digital Converter with JESD204B-compatible Serial Output |
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Subclass 1 deterministic latency |
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SNR = 70.6.5 dBFS @ 185 MHz |
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SFDR = 88 dBc @ 185 MHz |
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Total power: 711 mW |
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IF sampling frequencies to 400 MHz |
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Small package outline: 7 mm x 7 mm 48-Lead LFCSP |
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Learn more about the AD9250 dual-channel ADC
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| Low-jitter RF Clock Optimizes High-speed Data Converter SNR Performance in Communications and Instrumentation Applications |
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RMS jitter:
83 fs @ 245.76 MHZ (1 kHz to 100 MHz)
46 fs @ 245.76 MHz (12 kHz to 20 MHz)
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Maximum output speed: 3.6 GHz |
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Output-to-output skew: 25 ps |
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Number of outputs: 8 LVPECL and 1 LVPECL SYNC |
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7 mm x 7 mm 48-Lead LFCSP |
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Learn more about the AD9525 RF clock
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| Fractional-N/Integer-N PLL Synthesizer |
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RF bandwidth to 4 GHz |
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2.7 V to 3.3 V power supply |
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Separate VP allows extended tuning voltage |
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Programmable fractional modulus |
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Programmable charge pump current |
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3-wire serial interface |
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Analog and digital lock detect |
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Power-down mode |
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Pin-compatible with ADF4106/ADF4110/ADF4111/ADF4112/ ADF4113 and ADF4153 |
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Consistent RF output phase |
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Learn more and order samples of the ADF4153A PLL Synthesizer
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| Direct Digital Synthesizers with 12-Bit DAC |
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3.5 GSPS (AD9914) and 2.5 GSPS (AD9915) internal clock speed |
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Integrated 12-bit DAC |
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Frequency tuning resolution to 190 pHz (AD9914) and 135 pHz (AD9915) |
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16-bit phase tuning resolution |
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12-bit amplitude scaling |
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Programmable modulus |
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Automatic linear and nonlinear frequency sweeping capability |
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32-bit parallel data path interface |
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8 frequency/phase offset profiles |
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Learn more and order samples of the AD9914 and AD9915 Direct Digital Synthesizers
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Winter 2012 |
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Circuits From the Lab™ Reference Circuits |
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Increasing the Number of Outputs from a Clock Source Using Low Jitter LVPECL Fanout Buffers
Many systems require low jitter multiple system clocks for mixed signal processing and timing. This circuit interfaces the ADF4351 integrated phase-locked loop (PLL) and voltage-controlled oscillator (VCO) to the ADCLK948, which provides up to eight differential, low voltage, positive emitter coupled logic (LVPECL) outputs from one differential output of the ADF4351.
Read the circuit note and download design files |
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