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Data Converter news
and resources from the world leader
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New Products in Full Production:
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| Dual 14-bit, 250 MSPS, A/D converter features a JESD204B-compatible serial output to simplify the high-speed data converter-to-FPGA interconnect design environment
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| Smallest Quad Channel Non-volatile digiPOT |
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| 12-bit, 1 MSPS, A/D SAR Converter with Flexible Power Management
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12- bit, 1 MSPS |
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Flexible power supply range: VDD 2.09 V to 5.25 V |
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Flexible Power/Throughput Rate Management:
• 564 µW at 500 kSPS (3V VDD)
• 19 µW at 5 kSPS (3V VDD) |
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DC Accuracy: +/-1 LSB INL |
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8-lead, 2 mm x 2 mm LFCSP package |
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Learn more about the AD7091 12-bit, 1 MSPS, A/D Converter
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| Precision Analog Microcontroller extends ARM Cortex™-M3 based series
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Single 24-bit Sigma Delta ADC |
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ENOB = 19.3Bits @50 SPS |
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Low Power ARM Cortex™-M3 core (290 µA/MHz)
• Power Down Mode (4µA: wake-up timer active)
• On-chip 12-bit DAC
• ±5 ppm/°C Internal Reference
• 128k Bytes Flash/EE Memory, 8kB SRAM
• Internal watch crystal for wake-up timer
• ±16 MHz Oscillator
• UART, I²C and 2 x SPI Serial I/O
• 16-bit PWM and GPIO Port |
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Low Cost Development Tools
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Learn more about the ADuCM361 precision analog microcontroller
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| 24-Bit Sigma Delta Converter doubles throughput rate with less power and better noise performance
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5 SPS to 250 kSPS output rate |
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17.2 noise free bits at 250 kSPS |
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22 noise free bits at 5 SPS |
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Up to 90 dB 50 Hz and 60 Hz rejection |
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7.8 mA total current consumption |
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2.5 V, ±2.5 ppm/°C reference |
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±2.5% internal oscillator |
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Learn more about the 250 kSPS Sigma Delta A/D converter
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| Dual, 16-bit, high dynamic range D/A converter provides a sample rate of 1600 MSPS, permitting multicarrier generation up to the Nyquist frequency.
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Low spurious and distortion:
• 6-carrier GSM ACLR = 79 dBc at 200 MHz IF
• SFDR > 85 dBc (bandwidth = 300 MHz) at ZIF |
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Selectable 2×, 4×, 8× interpolation filter |
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Low power architecture, fS/4 power saving coarse mixer |
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Multiple chip synchronization with fixed latency and data generator latency compensation |
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Input signal power detection function |
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Learn more about the AD9142 dual 16-bit high-speed DAC
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| UltraLow-jitter RF clock optimizes dynamic performance in high-speed data converters
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Ultralow RMS jitter:
• 83 fs @ 245.76 MHZ (1 kHz to 100 MHz)
• 46 fs @ 245.76 MHz (12 kHz to 20 MHz) |
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Maximum output speed: 3.6 GHz |
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Output-to-output skew: 25 ps |
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Number of outputs: 8 LVPECL and 1 LVPECL SYNC |
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Learn more about the AD9525 RF Clock
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| The ADAS3022 is a complete 16-bit, 1 MSPS, successive approximation-based analog-to-digital data acquisition system that is manufactured on Analog Devices, Inc., proprietary iCMOS® high voltage industrial process technology. The device integrates an 8-channel, low leakage multiplexer; a high-impedance programmable gain instrumentation amplifier (PGIA) stage with a high common-mode rejection; a precision, low drift 4.096 V reference and buffer; and a 16-bit charge-redistribution analog-to-digital converter (ADC) with successive approximation register (SAR) architecture. The ADAS3022 can resolve eight single-ended inputs or four fully differential inputs up to ±24.576 V when using ±15 V supplies. In addition, the device can accept the commonly used bipolar differential, bipolar single-ended, pseudo bipolar, or pseudo unipolar input signals thus enabling the use of almost any direct sensor interface.
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The ADAS3022 simplifies design challenges by eliminating signal buffering, level shifting, amplification/attenuation, common-mode rejection, settling time, or any of the other analog signal conditioning challenges while allowing smaller form factor, faster time to market, and lower costs.
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| Applications
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Winter 2012 |
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| Data
Conversion Online Knowledge Resource
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The Data Conversion Knowledge resource site addresses the various design fundamentals necessary to insure that a given data conversion stage operates as intended. New content is continuously being generated by ADI technologists and applications engineers and added to this resource library.
Here are three of the latest content additions:
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| This webinar will examine a contemporary receive signal chain and take a close look at selecting suitable data converters and their key specifications and the tradeoffs that must be made. |
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| Video
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Rapid Prototyping with JESD204B using FMC and Xilinx FPGAs
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| Analog Dialogue Article
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| ADI Capacitance-to-Digital Converter Technology in Healthcare Applications |
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| This article focuses on capacitance-to-digital converter (CDC) technology, which enables the use of high performance capacitance sensing in healthcare applications. |
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| Applications Note
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| AN-1098: Methodology for Narrow-Band Interface Design Between High Performance Differential Driver Amplifiers and ADCs |
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| By adopting a narrow band-pass antialiasing filter interface between the driver amplifier and the target ADC, the output noise of the amplifier outside of the intended Nyquist zone can be attenuated, thus helping to preserve the available SNR of the ADC by as much as several dB. This application note provides a methodology to allow users to design a more effective interface between high performance driver amplifiers and ADCs, including those with switched- capacitor inputs |
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As seen in EDN Magazine, ADI's
Rarely Asked Questions presents common application challenges presented
in a unique way.
Question: You referred to Current Transformers in a recent RAQ. What are they and how are they used? |
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| A 16-Bit, 6 MSPS SAR ADC System with Low Power Input Drivers and Reference Optimized for Multiplexed Applications (CN0307)
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| This reference circuit is a 16-bit, 6 MSPS, successive approximation (SAR) |
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| analog-to-digital converter (ADC) and differential-to-differential driver combination optimized for low noise (signal-to-noise ratio [SNR] = 88.6 dB) and low distortion (total harmonic distortion [THD] = -110 dBc) at low power. |
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