March 2014
Data converter news and resources from the world leader.
New High Speed Products in Full Production

Quad, 16-Bit, 125 MSPS ADC with JESD204B Serial Output

Optimized for outstanding dynamic performance and low power in applications where a small package size is critical.

Small footprint: four ADCs are contained in a small, 8 mm × 8 mm package
JESD204B output block supports up to
6.4 Gbps per lane and one, two, and four lane configurations
Low power of 198 mW per channel at
125 MSPS, two lanes
High dynamic range
  SNR = 79.9 dBFS at 16 MHz (VREF = 1.4 V)
  SNR = 78.1 dBFS at 64 MHz (VREF = 1.4 V)
  SFDR = 86 dBc to Nyquist (VREF = 1.4 V)
650 MHz analog full power input bandwidth

The AD9656 is production released with samples available. Learn more.

Dual, 16-Bit TxDAC+® Digital-to-Analog Converter

Optimized for direct conversion transmit applications, including complex digital modulation, input signal power detection, and gain, phase, and offset compensation.

Supports input data rate up to 575 MHz
Very small inherent latency variation: <2 DAC clock cycles
  6-carrier GSM ACLR = 79 dBc at 200 MHz IF
  SFDR > 85 dBc (bandwidth = 300 MHz)
at ZIF
Multiple chip synchronization capability
Fixed latency and data generator latency compensation

The AD9142A is production released with samples available. Learn more.

16-Channel, 65 MSPS, and 8-Channel, 125 MSPS, 14-Bit High Speed Analog-to-Digital Converters

Provide the lowest power in the smallest package size in their class to target industrial ultrasound, instrumentation, healthcare imaging, and defense electronics applications.

SFDR: 90 dBc (to Nyquist)
DNL: ±0.8 LSB (typical); INL: ±01.2 LSB
650 MHz full power analog bandwidth
Low power
  16-channel—58 mW per channel at
  8-channel—110 mW per channel at
125 MSPS
10 mm × 10 mm, 144-ball CSP BGA

The AD9249 is production released with samples available. Learn more.
The AD9681 is production released with samples available. Learn more.
CN0279: High IF Sampling Receiver Front End with Band-Pass Filter

The circuit shown in the figure below is a narrow, band-pass receiver front end based on the ADL5565 ultralow noise differential amplifier driver and the AD9642 14-bit, 250 MSPS analog-to-digital converter (ADC). The ADL5565 is an ideal driver for the AD9642, and the fully differential architecture through the band-pass filter and into the ADC provides good high frequency common-mode rejection, as well as minimizes second-order distortion products.
Read this circuit note and download the design files.
Featured Webcast
Designing Wideband Front Ends for GSPS Converters

As high speed analog-to-digital converter technology improves, so does the need to resolve very high intermediate frequencies (IF) accurately at high speeds. This poses two challenges—the converter design itself, and the front-end design that couples the signal content to the converter. This webcast explores these challenges and associated design solutions.
Featured Article
Dual-Loop Clock Generator Cleans Jitter, Provides Multiple High Frequency Outputs

As the speed and resolution of data converters continue to increase, the need for higher frequency sampling clock sources with lower phase noise is growing. The integrated phase noise (jitter) presented to the clock inputs is one of the many performance bottlenecks facing designers when they create cellular base stations, military radar systems, and other designs that require high speed, high performance clock signals.
Featured Video
High Speed Converters: What? Why? (and a Little How?)

As analog-to-digital conversion moves closer to the beginning of the high speed signal chain, the performance demands can get extreme. View this episode of Chalk Talk, in which Amelia Dalton of Electronic Engineering Journal chats with David Robertson, vice president of Analog Devices, about how to design high speed converters for today's most demanding applications.