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Data Converter news and resources from the world leader


New Products in Full Production:
Dual 14-bit, 250 MSPS, A/D converter features a JESD204B-compatible serial output to simplify the high-speed data converter-to-FPGA interconnect design environment
JESD204B coded serial digital output with Subclass 1 deterministic latency
SNR = 70.1 dBFS at 185 MHz AIN and 250 MSPS
SFDR = 86 dBc at 185 MHz AIN and 250 MSPS
IF sampling frequencies of up to 400 MHz
95 dB channel isolation/crosstalk
Low power and small package size
Learn more about the AD9250 dual 14-bit high-speed ADC
Learn more about the pin-compatible AD6673 dual 11-bit version of the AD9250

Smallest Quad Channel Non-volatile digiPOT
Quad channel 256 tap, I2C Interface
Nominal Resistance Tolerance: ±8% max
3 MHz Bandwidth
35 ppm/°C Temperature Coefficient (rheostat mode)
4 kV ESD protection
3 mm x 3 mm 16-lead LFCSP package
Full series of single/dual/quad, 128/256 tap, I²C/SPI versions
Learn more about the AD5143 and watch a video explaining the technology that solves linear gain mode.
See the entire series of digiPOTs

12-bit, 1 MSPS, A/D SAR Converter with Flexible Power Management
12- bit, 1 MSPS
Flexible power supply range: VDD 2.09 V to 5.25 V
Flexible Power/Throughput Rate Management:
  • 564 µW at 500 kSPS (3V VDD)
  • 19 µW at 5 kSPS (3V VDD)
DC Accuracy: +/-1 LSB INL
8-lead, 2 mm x 2 mm LFCSP package
Learn more about the AD7091 12-bit, 1 MSPS, A/D Converter

Precision Analog Microcontroller extends ARM Cortex™-M3 based series
Single 24-bit Sigma Delta ADC
ENOB = 19.3Bits @50 SPS
Low Power ARM Cortex™-M3 core (290 µA/MHz)
  • Power Down Mode (4µA: wake-up timer active)
  • On-chip 12-bit DAC
  • ±5 ppm/°C Internal Reference
    • 128k Bytes Flash/EE Memory, 8kB SRAM
    • Internal watch crystal for wake-up timer
    • ±16 MHz Oscillator
    • UART, I²C and 2 x SPI Serial I/O
    • 16-bit PWM and GPIO Port
Low Cost Development Tools
Learn more about the ADuCM361 precision analog microcontroller

24-Bit Sigma Delta Converter doubles throughput rate with less power and better noise performance
5 SPS to 250 kSPS output rate
17.2 noise free bits at 250 kSPS
22 noise free bits at 5 SPS
Up to 90 dB 50 Hz and 60 Hz rejection
7.8 mA total current consumption
2.5 V, ±2.5 ppm/°C reference
±2.5% internal oscillator
Learn more about the 250 kSPS Sigma Delta A/D converter

Dual, 16-bit, high dynamic range D/A converter provides a sample rate of 1600 MSPS, permitting multicarrier generation up to the Nyquist frequency.
Low spurious and distortion:
  • 6-carrier GSM ACLR = 79 dBc at 200 MHz IF
  • SFDR > 85 dBc (bandwidth = 300 MHz) at ZIF
Selectable 2×, 4×, 8× interpolation filter
Low power architecture, fS/4 power saving coarse mixer
Multiple chip synchronization with fixed latency and data generator latency compensation
Input signal power detection function
Learn more about the AD9142 dual 16-bit high-speed DAC

UltraLow-jitter RF clock optimizes dynamic performance in high-speed data converters
Ultralow RMS jitter:
  • 83 fs @ 245.76 MHZ (1 kHz to 100 MHz)
  • 46 fs @ 245.76 MHz (12 kHz to 20 MHz)
Maximum output speed: 3.6 GHz
Output-to-output skew: 25 ps
Number of outputs: 8 LVPECL and 1 LVPECL SYNC
Learn more about the AD9525 RF Clock

The ADAS3022 is a complete 16-bit, 1 MSPS, successive approximation-based analog-to-digital data acquisition system that is manufactured on Analog Devices, Inc., proprietary iCMOS® high voltage industrial process technology. The device integrates an 8-channel, low leakage multiplexer; a high-impedance programmable gain instrumentation amplifier (PGIA) stage with a high common-mode rejection; a precision, low drift 4.096 V reference and buffer; and a 16-bit charge-redistribution analog-to-digital converter (ADC) with successive approximation register (SAR) architecture. The ADAS3022 can resolve eight single-ended inputs or four fully differential inputs up to ±24.576 V when using ±15 V supplies. In addition, the device can accept the commonly used bipolar differential, bipolar single-ended, pseudo bipolar, or pseudo unipolar input signals thus enabling the use of almost any direct sensor interface.
The ADAS3022 simplifies design challenges by eliminating signal buffering, level shifting, amplification/attenuation, common-mode rejection, settling time, or any of the other analog signal conditioning challenges while allowing smaller form factor, faster time to market, and lower costs.
Applications
Multi-channel data acquisition and system monitoring
Process Control
Power line monitoring
Automated test equipment
Instrumentation
Learn more about the 16-bit, 8-channel, 1 MSPS ADAS3022 DAS

Winter 2012
Data Conversion Online Knowledge Resource
The Data Conversion Knowledge resource site addresses the various design fundamentals necessary to insure that a given data conversion stage operates as intended. New content is continuously being generated by ADI technologists and applications engineers and added to this resource library.
Here are three of the latest content additions:
MT-229 Quantization Noise: An Expanded Derivation of the Equation, SNR = 6.02 N + 1.76 dB
Making Batteries Last Longer with Fast, High-Precision SAR Analog-to-Digital Converters
Precision basics: How not to be surprised by unexpected error sources
We welcome you to visit this site and learn about designing the complete conversion signal chain.
Webcast on-demand
Fundamentals of Data Conversion in Receivers
This webinar will examine a contemporary receive signal chain and take a close look at selecting suitable data converters and their key specifications and the tradeoffs that must be made.
Video
Rapid Prototyping with JESD204B using FMC and Xilinx FPGAs
See it in action: A faster, easier way to connect your Xilinx Kintex and Virtex FPGAs with ADI's AD9250 JESD204B data converter.
Analog Dialogue Article
ADI Capacitance-to-Digital Converter Technology in Healthcare Applications
This article focuses on capacitance-to-digital converter (CDC) technology, which enables the use of high performance capacitance sensing in healthcare applications.
Read the complete article here
Applications Note
AN-1098: Methodology for Narrow-Band Interface Design Between High Performance Differential Driver Amplifiers and ADCs
By adopting a narrow band-pass antialiasing filter interface between the driver amplifier and the target ADC, the output noise of the amplifier outside of the intended Nyquist zone can be attenuated, thus helping to preserve the available SNR of the ADC by as much as several dB. This application note provides a methodology to allow users to design a more effective interface between high performance driver amplifiers and ADCs, including those with switched- capacitor inputs
Read the complete article here
Get answers to your design questions in our EngineerZone Data Converters support community
As seen in EDN Magazine, ADI's Rarely Asked Questions presents common application challenges presented in a unique way.

Question: You referred to Current Transformers in a recent RAQ. What are they and how are they used?
View Answer
A 16-Bit, 6 MSPS SAR ADC System with Low Power Input Drivers and Reference Optimized for Multiplexed Applications (CN0307)
This reference circuit is a 16-bit, 6 MSPS, successive approximation (SAR) Circuits from the Lab
analog-to-digital converter (ADC) and differential-to-differential driver combination optimized for low noise (signal-to-noise ratio [SNR] = 88.6 dB) and low distortion (total harmonic distortion [THD] = -110 dBc) at low power.
Read this circuit note and download design files
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