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Oscilloscopes

Minimizing Clock Jitter

  • AN-756: Sampled Systems and the Effects of Clock Phase Noise and Jitter (pdf)
  • MT-008: Converting Oscillator Phase Noise to Time Jitter (pdf)
  • ADIsimCLK: Tool to predict phase noise and jitter for ADI clock products
  • CN0003: Very Low Jitter Encode (Sampling) Clocks for High Speed Analog-to-Digital Converters Using the ADF4002 PLL
  • AN-823: Direct Digital Synthesizers in Clocking Applications (pdf)
  • Analog-to-Digital Converter Clock Optimization: A Test Engineering Perspective
  • AN-501: Aperture Uncertainty and ADC System Performance (pdf)
  • How to Determine an Effective Damping Factor for a Third-Order PLL (pdf)
  • AN-837: DDS-Based Clock Jitter Performance vs. DAC Reconstruction Filter Performance (pdf)
  • CN0109: Low Jitter Sampling Clock Generator for High Performance ADCs Using the AD9958/AD9858 500 MSPS/1GSPS DDS and AD9515 Clock Distribution IC
  • Clocking Requirements for High Speed Data Converters
  • Understand the Effects of Clock Jitter and Phase Noise on Sampled Systems
  • Clock Requirements For Data Converters
  • Design A Clock-Distribution Strategy With Confidence
  • Speedy A/Ds Demand Stable Clocks
  • Single-Chip Clock Generator with 14-Channel Distribution Solves Timing Challenges in Networks
  • Termination of High-Speed Converter Clock Distribution Devices