#include<cdefbf537.h>
#include<stdio.h>
#include<sysreg.h>
#include<ccblkfn.h>
#include <sys\exception.h>

void Init_PLL(void);
void Init_ASYNC_Memory(void);
void Init_GPIO(void);
void Enable_Interrupt(void);
void Fill_Master_Bufer(void);
void HDMA_Config(void);
void Data_Transfer(void);
EX_INTERRUPT_HANDLER(PG13_ISR);


/*
PLL Configuration 
-----------------
CLKIN on EZ-Kit is 25MHz. This value gives CCLK = 500MHz and SCLK = 100MHz.
*/


#define MSELECT ( 20 << 9 )		// Ensure that CLKIN*MSELECT = VCO Max.		
#define CSELECT ( 0  << 4 )		// Valid CSEL Values: 1,2,4,8
#define SSELECT ( 5 )			// Valid SSEL Values: 1-15



/************ #define of control and data address on ASYNC Bank3 ****************/

#define DATA_READ_WRITE_ADDR 	0x20300000
#define CONFIG_READ_WRITE_ADDR 	0x20300800

#define pDATA_READ_WRITE_ADDR 	 ((unsigned char *)DATA_READ_WRITE_ADDR)
#define pCONFIG_READ_WRITE_ADDR  ((unsigned short *)CONFIG_READ_WRITE_ADDR)


/****************************************************************************/


#define Transfer_Size 64
#define HOST_READ

short HDMA_Config_Words[7] = 
					{ 
						#ifdef HOST_READ		
						0x10A9,
						#else					//HOST_CONFIG
						0x10AB,
						#endif

						0x0000,					//START ADDRESS. L
						0xFF80,					//START ADDRESS. H
						(Transfer_Size/4),		//X-Count
						4,						//X-Modify
						0,						//Y-Count
						0						//Y-Modify
					};


/************************************************************************/

char Master_Buffer[Transfer_Size];
unsigned short i, j, data, ISR_Count = 0;
