#include "config.h"

.section L1_code;
.global _main;

_main:
		
				p0.l = lo(PORTD_MUX);
				p0.h = hi(PORTD_MUX);
				r0.h = 0x5555;
				r0.l = 0x1234;
				w[p0] = r0;
	
	
			R6 = 0;	// ISR count
			
			call Init_PLL;
			
			
			#ifdef HOST_READ
			
			call Fill_Slave_Buffer;
						
			#endif
			
			
			call GP_PORT_Config;
			call Enable_Interrupts;
			call Host_Config;
			
			
			here: nop;
			jump here;
			
_main.end:

/************************************************************************/

Init_PLL:


			//configure CCLK and SCLK to 500 and 100 MHz respectively.
			// CLKIN on EZ-Kit is 25MHz.
			
			CLI R0;
			
			P0.L = LO(PLL_CTL);
			P0.H = HI(PLL_CTL);
			R0.L = 0x2800;			//25MHz * 20 = 500MHz
			W[P0] = R0.L;
			ssync;
					
			IDLE;
			
			STI R0;
			
			P0.L = LO(PLL_DIV);
			P0.H = HI(PLL_DIV);
			R0.L = 0x5;				
			W[P0] = R0.L;
			ssync;
			
			RTS;
			
Init_PLL.end:
			
/**************************************************************************/

GP_PORT_Config:

			
			// Enable HD0-HD15

			P0.L = LO(PORTD_FER);
			P0.H = HI(PORTD_FER);
			R0.L = 0xFFFF;
			W[P0] = R0.L;
			ssync;
			
			
			P0.L = LO(PORTD_MUX);
			P0.H = HI(PORTD_MUX);
			R0.L = 0x5555;			//2nd function
			R0.H = 0x5555;
			[P0] = R0;
			ssync;
			
			// Enable HCE, HWR, HRD, 
			
			P0.L = LO(PORTG_FER);
			P0.H = HI(PORTG_FER);
			R0.L = PG5 | PG6 | PG7;
			W[P0] = R0.L;
			ssync;
			
			P0.L = LO(PORTG_MUX);
			P0.H = HI(PORTG_MUX);
			R0.L = 0x5400;			//2nd function
			W[P0] = R0.L;
			ssync;
			
			// Enable HADDR, HACK, 
			
			P0.L = LO(PORTH_FER);
			P0.H = HI(PORTH_FER);
			R0.L = PH3 | PH4;
			W[P0] = R0.L;
			ssync;
			
			P0.L = LO(PORTH_MUX);
			P0.H = HI(PORTH_MUX);
			R0.L = 0x0000;			//1st function
			W[P0] = R0.L;
			ssync;
			
			rts;

			
GP_PORT_Config.end:



/*****************************************************************************/			
		
Host_Config:


			P1.L = LO(HOST_CONTROL);
			P1.H = HI(HOST_CONTROL);
			
			R0.L = EHR | EHW | INT_MODE | HOSTDP_DATA_SIZE | HOSTDP_EN;
			
			W[P1] = R0.L;
			ssync;
			
			rts;
			
Host_Config.end:

/*****************************************************************************/			


Fill_Slave_Buffer:

			// fill the buffer so that host reads this data
			
			R0 =0;
			P0.L = LO(Slave_Buffer);
			P0.H = HI(Slave_Buffer);
			
			P1 = Transfer_Size;	// Array size
			
			Lsetup(start, end) LC0 = P1;
			
			R0.L = 0xA5A5;
			
			start: 
			
				W[P0++] = R0;
												
			end: R0 = ~R0;

			rts;

fill_buffer.end:

						
/*****************************************************************************/			



Enable_Interrupts:
			
			[--SP] = RETS;
			
			// Map the vector table to the HOST_ISR address.
		
			P0.L = LO(EVT9);
			P0.H = HI(EVT9);
			R0.L = LO(HOSTDP_ISR);		//Default IAR value for HOSTDP 
			R0.H = HI(HOSTDP_ISR);
			[ P0 ] = R0;
			ssync;
			
			
			// Enable HOSTDP at SIC level
		
			P0.L = lo(SIC_IMASK1);
			P0.H = hi(SIC_IMASK1);
			R0 = 0;
			bitset(R0,6);
			[P0] = R0;		
			ssync;
		
			// Enable interrupts IVG9
		
			P0.L = LO(IMASK);
			P0.H = HI(IMASK);
			R0.H = 0; 
			R0.L = EVT_IVG9 ;
			[ P0 ] = R0;
			ssync;
			
			RETS = [SP++];
		
			RTS;
			
Enable_Interrupts.end:
			
/***********************************************************/			
						
HOSTDP_ISR:

			R6+= 1;
			
			P3.L = LO(DMA14_IRQ_STATUS);
			P3.H = HI(DMA14_IRQ_STATUS);
			R1.L = DMA_DONE;
			W[P3] = R1.L;
			ssync;
			
				
			RTI;

HOSTDP_ISR.end:
			
			
/*******************************************************************/			
		