*********************************************************************************************************************************


This directory is associated with Rev 5 of the Application Note


    Expert Code Generator for SHARC® Processors (EE-322) 


that can be found at http://www.analog.com/en/embedded-processing-dsp/sharc/processors/application-notes/resources/index.html


Analog Devices, Inc.
DSP Division
Three Technology Way
P.O. Box 9106
Norwood, MA 02062

Date Created:    Jan 13th, 2012

*********************************************************************************************************************************

Description of the EE-Note:

The ADSP-214xx family of SHARC® processors includes new modules and enhanced features as compared to the older family of SHARC® 
processors. Some important new blocks include the Double Data Rate 2 (DDR2) controller (2146x only), the Finite Impulse Response 
(FIR), Infinite Impulse Response (IIR), and Fast Fourier Transform (FFT) hardware accelerators. Expert Code Generator can be used 
to generate code for initializing these blocks to your system’s requirements. In addition, Expert Code Generator also produces 
initialization code for the Phase-Locked Loop (PLL), SDRAM, and Asynchronous Memory Interface (AMI) controllers both for new and 
the older SHARC® processors (2126x onwards). Expert Code Generator consists of two utilities that can be directly integrated as 
plug-ins to VisualDSP++® environment:

1) Code generator for initializing PLL, DDR2/SDRAM, and AMI controllers
2) Code generator for FIR, IIR, and FFT accelerators



*********************************************************************************************************************************

This folder includes four subfolders:

1) PLL_DDR2_SDRAM_AMI: Has example codes in both Assembly and C for Initializing PLL, DDR2/SDRAM, and AMI controllers tested on 
		       EZ-Kits corresponding to various SHARC families (2126x, 2136x, 21367/8/9, 214xx).

2) Accelerators:       Has example codes in both Assembly and C for using the Plug-in generated source files for FIR/IIR/FFT 
		       accelerators on 214xx processors.

The code examples have been written and tested with 

VisualDSP++ 5.0 Update 10,

ADSP-21262 EZ-Kit Rev 1.5, Si rev 0.1

ADSP-21364 EZ-Kit Rev 2.0, Si rev 0.5

ADSP-21369 EZ-Kit Rev 2.1, Si rev 0.2

ADSP-21375 EZ-Kit Rev 1.0, Si rev 0.0

ADSP-21469 EZ-Kit Rev 0.1, Si rev 0.0

ADSP-21479 EZ-Kit Rev 0.1, Si rev 0.0

ADSP-21489 EZ-Kit Rev 0.1, Si rev 0.1

 
*********************************************************************************************************************************

