
#define INDIV0 0
#define INDIV1 INDIV

#define DLL_LOCKED BIT_30

/*******************************************************************************************************************************/
/*												PLL (2126x and 2136x processors	)								  			    */
/*******************************************************************************************************************************/

/* 	(1)

	Description: Configures the PLL in software to generate CCLK values

 	Arguments:

	Parameter 			Description			  			Valid Values

    Multiplier			Multiplier value	  			1 to 64
    Divider	 			Divider	value		  			2, 4, 8, 16
    Input_Divider		Input divider enable/disable	1.0
*/

#ifdef _LANGUAGE_C


#define ADSP_2126x_2136x_PLL_Init(Multiplier, Divider, Input_Divider)\
	int cs_temp,cs_i;\
	cs_temp=PLLM##Multiplier|PLLD##Divider|INDIV##Input_Divider|DIVEN;\
	*pPMCTL=cs_temp;\
	cs_temp|=PLLBP;\
	cs_temp^=DIVEN;\
	*pPMCTL=cs_temp;\
	for(cs_i=0;cs_i<4096;cs_i++)\
	asm("nop;");\
	cs_temp=*pPMCTL;\
	cs_temp^=PLLBP;\
	*pPMCTL=cs_temp;\
	for(cs_i=0;cs_i<16;cs_i++)\
	asm("nop;");

#else


#define ADSP_2126x_2136x_PLL_Init(Multiplier, Divider, Input_Divider)\
	ustat3 = PLLM##Multiplier|PLLD##Divider|INDIV##Input_Divider|DIVEN;\
	dm(PMCTL) = ustat3;\
	bit set ustat3 PLLBP;\
	bit clr ustat3 DIVEN;\
	dm(PMCTL) = ustat3;\
	lcntr = 4096, do wait_here? until lce;\
	wait_here?: nop;\
	ustat3 = dm(PMCTL);\
	bit clr ustat3 PLLBP;\
	dm(PMCTL) = ustat3;\
	lcntr = 16, do wait_here1? until lce;\
	wait_here1?: nop;

#endif


/*******************************************************************************************************************************/
/*												PLL (21367/8/9 and 21237x processors	)	             			  			   */
/*******************************************************************************************************************************/

/* 	(1)

	Description: Configures the PLL in software to generate CCLK values

 	Arguments:

	Parameter 			Description			  			Valid Values

    Multiplier			Multiplier value	  			1 to 64
    Divider	 			Divider	value		  			1, 2, 4, 8
    Input_Divider		Input divider enable/disable	1.0
    CCLK_SDCLK_ratio 	Core clock to SDCLK ratio		2, 2_5, 3,3_5, 4

*/

#ifdef _LANGUAGE_C


#define ADSP_21369_2137x_PLL_Init(Multiplier, Divider, Input_Divider, CCLK_SDCLK_ratio)\
	int cs_temp,cs_i;\
	cs_temp=PLLM##Multiplier|PLLD##Divider|INDIV##Input_Divider|SDCKR##CCLK_SDCLK_ratio|DIVEN;\
	*pPMCTL=cs_temp;\
	cs_temp|=PLLBP;\
	cs_temp^=DIVEN;\
	*pPMCTL=cs_temp;\
	for(cs_i=0;cs_i<4096;cs_i++)\
	asm("nop;");\
	cs_temp=*pPMCTL;\
	cs_temp^=PLLBP;\
	*pPMCTL=cs_temp;\
	for(cs_i=0;cs_i<16;cs_i++)\
	asm("nop;");

#else


#define ADSP_21369_2137x_PLL_Init(Multiplier, Divider, Input_Divider, CCLK_SDCLK_ratio)\
	ustat3 = PLLM##Multiplier|PLLD##Divider|INDIV##Input_Divider|DIVEN;\
	bit set ustat3 SDCKR##CCLK_SDCLK_ratio;\
	dm(PMCTL) = ustat3;\
	bit set ustat3 PLLBP;\
	bit clr ustat3 DIVEN;\
	dm(PMCTL) = ustat3;\
	lcntr = 4096, do wait_here? until lce;\
	wait_here?: nop;\
	ustat3 = dm(PMCTL);\
	bit clr ustat3 PLLBP;\
	dm(PMCTL) = ustat3;\
	lcntr = 16, do wait_here1? until lce;\
	wait_here1?: nop;

#endif




/*******************************************************************************************************************************/
/*												PLL (2146x processors	)												       */
/*******************************************************************************************************************************/

/* 	(1)

	Description: Configures the PLL in software to generate CCLK, DDR2CLK, MLBCLK, LPCLK values

 	Arguments:

	Parameter 			Description			  			Valid Values

    Multiplier			Multiplier value	  			1 to 64
    Divider	 			Divider	value		  			2, 4, 8, 16
    Input_Divider		Input divider enable/disable	1.0
    CCLK_DDCLK_ratio 	Core clock to SDCLK ratio		2, 3, 4
	CCLK_LPCLK_ratio	Core clock to LPCLK ratio		2, 2_5, 3, 4
	CCLK_MLBCLK_ratio	Core clock to MLBCLK ratio		4
*/

#ifdef _LANGUAGE_C

#define ADSP_2146X_PLL_Init(Multiplier, Divider, Input_Divider, CCLK_DDR2CLK_ratio,CCLK_LPCKR_ratio)\
	int cs_temp,cs_i;\
	cs_temp=*pPMCTL;\
	cs_temp&=~PLLD16 ;\
	cs_temp|=(PLLD4 | DIVEN) ;\
	*pPMCTL = cs_temp;\
	for(cs_i=0;cs_i<16;cs_i++);\
	cs_temp&=~DIVEN;\
	cs_temp|=(INDIV | PLLBP);\
	*pPMCTL = cs_temp;\
	for(cs_i=0;cs_i<4096;cs_i++);\
	cs_temp=*pPMCTL;\
	cs_temp&=~PLLBP;\
	*pPMCTL = cs_temp;\
	for(cs_i=0;cs_i<16;cs_i++);\
	cs_temp = *pPMCTL;\
	cs_temp&=~ (INDIV | PLLM63);\
	cs_temp|= (PLLM##Multiplier | PLLBP | INDIV##Input_Divider);\
	*pPMCTL = cs_temp;\
	for(cs_i=0;cs_i<4096;cs_i++);\
	cs_temp = *pPMCTL;\
	cs_temp&=~PLLBP;\
	*pPMCTL=cs_temp;\
	for(cs_i=0;cs_i<16;cs_i++);\
	cs_temp=*pPMCTL;\
	cs_temp&=~(PLLD16 | 0x1C0000 | LPCKR4 );\
	cs_temp|= (DDR2CKR##CCLK_DDR2CLK_ratio | LPCKR##CCLK_LPCKR_ratio | PLLD##Divider | DIVEN);\
	*pPMCTL=cs_temp;\
	for(cs_i=0;cs_i<16;cs_i++);

#define ADSP_2146X_PLL_Init_DDR2CKR4_PLLD4(Multiplier, Input_Divider, CCLK_LPCKR_ratio)\
	int cs_temp,cs_i;\
	cs_temp=*pPMCTL;\
	cs_temp&=~PLLD16 ;\
	cs_temp|=(PLLD8 | DIVEN) ;\
	*pPMCTL = cs_temp;\
	for(cs_i=0;cs_i<16;cs_i++);\
	cs_temp&=~DIVEN;\
	cs_temp|=(INDIV | PLLBP);\
	*pPMCTL = cs_temp;\
	for(cs_i=0;cs_i<4096;cs_i++);\
	cs_temp=*pPMCTL;\
	cs_temp&=~PLLBP;\
	*pPMCTL = cs_temp;\
	for(cs_i=0;cs_i<16;cs_i++);\
	cs_temp = *pPMCTL;\
	cs_temp&=~ (INDIV | PLLM63);\
	cs_temp|= (PLLM##Multiplier | PLLBP | INDIV##Input_Divider);\
	*pPMCTL = cs_temp;\
	for(cs_i=0;cs_i<4096;cs_i++);\
	cs_temp = *pPMCTL;\
	cs_temp&=~PLLBP;\
	*pPMCTL=cs_temp;\
	for(cs_i=0;cs_i<16;cs_i++);\
	cs_temp=*pPMCTL;\
	cs_temp&=~(PLLD16 | 0x1C0000 | LPCKR4 );\
	cs_temp|= (PLLD4 | DDR2CKR4 | LPCKR##CCLK_LPCKR_ratio  | DIVEN);\
	*pPMCTL=cs_temp;\
	for(cs_i=0;cs_i<16;cs_i++);

#define ADSP_2146X_PLL_Init_INDIV_STEP_NOT_REQUIRED(Multiplier, Divider, Input_Divider, CCLK_DDR2CLK_ratio,CCLK_LPCKR_ratio)\
	int cs_temp,cs_i;\
	cs_temp=*pPMCTL;\
	cs_temp&=~PLLD16 ;\
	cs_temp|=(PLLD4 | DIVEN) ;\
	*pPMCTL = cs_temp;\
	for(cs_i=0;cs_i<16;cs_i++);\
	cs_temp = *pPMCTL;\
	cs_temp&=~ (INDIV | PLLM63);\
	cs_temp|= (PLLM##Multiplier | PLLBP | INDIV##Input_Divider);\
	*pPMCTL = cs_temp;\
	for(cs_i=0;cs_i<4096;cs_i++);\
	cs_temp = *pPMCTL;\
	cs_temp&=~PLLBP;\
	*pPMCTL=cs_temp;\
	for(cs_i=0;cs_i<16;cs_i++);\
	cs_temp=*pPMCTL;\
	cs_temp&=~(PLLD16 | 0x1C0000 | LPCKR4 );\
	cs_temp|= (DDR2CKR##CCLK_DDR2CLK_ratio | LPCKR##CCLK_LPCKR_ratio | PLLD##Divider | DIVEN);\
	*pPMCTL=cs_temp;\
	for(cs_i=0;cs_i<16;cs_i++);

#define ADSP_2146X_PLL_Init_DDR2CKR4_PLLN4_INDIV_STEP_NOT_REQUIRED(Multiplier, Input_Divider, CCLK_LPCKR_ratio)\
	int cs_temp,cs_i;\
	cs_temp=*pPMCTL;\
	cs_temp&=~PLLD16 ;\
	cs_temp|=(PLLD8 | DIVEN) ;\
	*pPMCTL = cs_temp;\
	for(cs_i=0;cs_i<16;cs_i++);\
	cs_temp = *pPMCTL;\
	cs_temp&=~ (INDIV | PLLM63);\
	cs_temp|= (PLLM##Multiplier | PLLBP | INDIV##Input_Divider);\
	*pPMCTL = cs_temp;\
	for(cs_i=0;cs_i<4096;cs_i++);\
	cs_temp = *pPMCTL;\
	cs_temp&=~PLLBP;\
	*pPMCTL=cs_temp;\
	for(cs_i=0;cs_i<16;cs_i++);\
	cs_temp=*pPMCTL;\
	cs_temp&=~(PLLD16 | 0x1C0000 | LPCKR4 );\
	cs_temp|= (PLLD4 | DDR2CKR4 | LPCKR##CCLK_LPCKR_ratio | DIVEN);\
	*pPMCTL=cs_temp;\
	for(cs_i=0;cs_i<16;cs_i++);

#else

#define ADSP_2146X_PLL_Init(Multiplier, Divider, Input_Divider, CCLK_DDR2CLK_ratio,CCLK_LPCKR_ratio)\
	ustat1 = dm(PMCTL);\
	bit clr USTAT1  PLLD16 ;\
	bit set USTAT1  PLLD4 | DIVEN ;\
	dm(PMCTL) = ustat1;\
	lcntr=16, do first_div_delay? until lce;\
	first_div_delay?: nop;\
	bit clr ustat1 DIVEN;\
	bit set ustat1 INDIV | PLLBP;\
	dm(PMCTL) = ustat1;\
	lcntr=4096, do first_bypass_delay? until lce;\
	first_bypass_delay?:nop;\
	ustat1 = dm(PMCTL);\
	bit clr ustat1 PLLBP;\
	dm(PMCTL) = ustat1;\
	lcntr=16, do second_div_delay? until lce;\
	second_div_delay?:nop;\
	ustat1 = dm(PMCTL);\
	bit clr ustat1 INDIV | PLLM63;\
	bit set ustat1 PLLM##Multiplier | INDIV##Input_Divider | PLLBP;\
	dm(PMCTL) = ustat1;\
	lcntr=4096, do second_bypass_delay? until lce;\
	second_bypass_delay?:nop;\
	ustat1 = dm(PMCTL);\
	bit clr ustat1 PLLBP;\
	dm(PMCTL) = ustat1;\
	lcntr=16, do third_div_delay? until lce;\
	third_div_delay?:nop;\
	ustat1 = dm(PMCTL);\
	bit clr ustat1 PLLD16 | 0x1C0000 | LPCKR4 ;\
	bit set ustat1 DDR2CKR##CCLK_DDR2CLK_ratio | LPCKR##CCLK_LPCKR_ratio | PLLD##Divider | DIVEN;\
	dm(PMCTL) = ustat1;\
	lcntr=16, do fourth_div_delay? until lce;\
	fourth_div_delay?: nop;


#define ADSP_2146X_PLL_Init_DDR2CKR4_PLLN4(Multiplier, Input_Divider, CCLK_LPCKR_ratio)\
	ustat1 = dm(PMCTL);\
	bit clr USTAT1  PLLD16 ;\
	bit set USTAT1  PLLD8 | DIVEN ;\
	dm(PMCTL) = ustat1;\
	lcntr=16, do first_div_delay? until lce;\
	first_div_delay?: nop;\
	bit clr ustat1 DIVEN;\
	bit set ustat1 INDIV | PLLBP;\
	dm(PMCTL) = ustat1;\
	lcntr=4096, do first_bypass_delay? until lce;\
	first_bypass_delay?:nop;\
	ustat1 = dm(PMCTL);\
	bit clr ustat1 PLLBP;\
	dm(PMCTL) = ustat1;\
	lcntr=16, do second_div_delay? until lce;\
	second_div_delay?:nop;\
	ustat1 = dm(PMCTL);\
	bit clr ustat1 INDIV | PLLM63;\
	bit set ustat1 PLLM##Multiplier | INDIV##Input_Divider | PLLBP;\
	dm(PMCTL) = ustat1;\
	lcntr=4096, do second_bypass_delay? until lce;\
	second_bypass_delay?:nop;\
	ustat1 = dm(PMCTL);\
	bit clr ustat1 PLLBP;\
	dm(PMCTL) = ustat1;\
	lcntr=16, do third_div_delay? until lce;\
	third_div_delay?:nop;\
	ustat1 = dm(PMCTL);\
	bit clr ustat1 PLLD16 | 0x1C0000 | LPCKR4 ;\
	bit set ustat1 DDR2CKR4 | LPCKR##CCLK_LPCKR_ratio | PLLD4 | DIVEN;\
	dm(PMCTL) = ustat1;\
	lcntr=16, do fourth_div_delay? until lce;\
	fourth_div_delay?: nop;

#define ADSP_2146X_PLL_Init_INDIV_STEP_NOT_REQUIRED(Multiplier, Divider, Input_Divider, CCLK_DDR2CLK_ratio,CCLK_LPCKR_ratio)\
	ustat1 = dm(PMCTL);\
	bit clr USTAT1  PLLD16 ;\
	bit set USTAT1  PLLD4 | DIVEN ;\
	dm(PMCTL) = ustat1;\
	lcntr=16, do first_div_delay? until lce;\
	first_div_delay?: nop;\
	ustat1 = dm(PMCTL);\
	bit clr ustat1 INDIV | PLLM63;\
	bit set ustat1 PLLM##Multiplier | INDIV##Input_Divider | PLLBP;\
	dm(PMCTL) = ustat1;\
	lcntr=4096, do second_bypass_delay? until lce;\
	second_bypass_delay?:nop;\
	ustat1 = dm(PMCTL);\
	bit clr ustat1 PLLBP;\
	dm(PMCTL) = ustat1;\
	lcntr=16, do third_div_delay? until lce;\
	third_div_delay?:nop;\
	ustat1 = dm(PMCTL);\
	bit clr ustat1 PLLD16 | 0x1C0000 | LPCKR4 ;\
	bit set ustat1 DDR2CKR##CCLK_DDR2CLK_ratio | LPCKR##CCLK_LPCKR_ratio | PLLD##Divider | DIVEN;\
	dm(PMCTL) = ustat1;\
	lcntr=16, do fourth_div_delay? until lce;\
	fourth_div_delay?: nop;

#define ADSP_2146X_PLL_Init_DDR2CKR4_PLLN4_INDIV_STEP_NOT_REQUIRED(Multiplier, Input_Divider, CCLK_LPCKR_ratio)\
	ustat1 = dm(PMCTL);\
	bit clr USTAT1  PLLD16 ;\
	bit set USTAT1  PLLD8 | DIVEN ;\
	dm(PMCTL) = ustat1;\
	lcntr=16, do first_div_delay? until lce;\
	first_div_delay?: nop;\
	ustat1 = dm(PMCTL);\
	bit clr ustat1 INDIV | PLLM63;\
	bit set ustat1 PLLM##Multiplier | INDIV##Input_Divider | PLLBP;\
	dm(PMCTL) = ustat1;\
	lcntr=4096, do second_bypass_delay? until lce;\
	second_bypass_delay?:nop;\
	ustat1 = dm(PMCTL);\
	bit clr ustat1 PLLBP;\
	dm(PMCTL) = ustat1;\
	lcntr=16, do third_div_delay? until lce;\
	third_div_delay?:nop;\
	ustat1 = dm(PMCTL);\
	bit clr ustat1 PLLD16 | 0x1C0000 | LPCKR4 ;\
	bit set ustat1 DDR2CKR4 | LPCKR##CCLK_LPCKR_ratio | PLLD4 | DIVEN;\
	dm(PMCTL) = ustat1;\
	lcntr=16, do fourth_div_delay? until lce;\
	fourth_div_delay?: nop;

#endif


/*******************************************************************************************************************************/
/*												PLL (2147x and 2148x processors	)	             			  			       */
/*******************************************************************************************************************************/

/* 	(1)

	Description: Configures the PLL in software to generate CCLK values

 	Arguments:

	Parameter 			Description			  			Valid Values

    Multiplier			Multiplier value	  			1 to 64
    Divider	 			Divider	value		  			1, 2, 4, 8
    Input_Divider		Input divider enable/disable	1.0
    CCLK_SDCLK_ratio 	Core clock to SDCLK ratio		2, 2_5, 3,3_5, 4
    CCLK_MLBCLK_ratio 	Core clock to MLBCLK ratio		4

*/

#ifdef _LANGUAGE_C

#define ADSP_2147x_2148x_PLL_Init(Multiplier, Divider,Input_Divider, CCLK_SDCLK_ratio)\
	int cs_temp,cs_i;\
	cs_temp=*pPMCTL;\
	cs_temp&=~PLLD16 ;\
	cs_temp|= PLLD4 | DIVEN ;\
	*pPMCTL = cs_temp;\
	for(cs_i=0;cs_i<16;cs_i++);\
	cs_temp&=~DIVEN;\
	cs_temp|=(INDIV | PLLBP);\
	*pPMCTL = cs_temp;\
	for(cs_i=0;cs_i<4096;cs_i++);\
	cs_temp=*pPMCTL;\
	cs_temp&=~PLLBP;\
	*pPMCTL = cs_temp;\
	for(cs_i=0;cs_i<16;cs_i++);\
	cs_temp = *pPMCTL;\
	cs_temp&=~(INDIV | PLLM63);\
	cs_temp|= (PLLM##Multiplier | INDIV##Input_Divider | PLLBP);\
	*pPMCTL = cs_temp;\
	for(cs_i=0;cs_i<4096;cs_i++);\
	cs_temp = *pPMCTL;\
	cs_temp&=~PLLBP;\
	*pPMCTL=cs_temp;\
	for(cs_i=0;cs_i<16;cs_i++);\
	cs_temp=*pPMCTL;\
	cs_temp&=~(PLLD16 | SDCKR3_5 | SDCKR4 );\
	cs_temp|= (PLLD##Divider | SDCKR##CCLK_SDCLK_ratio | DIVEN);\
	*pPMCTL=cs_temp;\
	for(cs_i=0;cs_i<16;cs_i++);

#define ADSP_2147x_2148x_PLL_Init_SDCKR4_PLLN4(Multiplier, Input_Divider)\
	int cs_temp,cs_i;\
	cs_temp=*pPMCTL;\
	cs_temp&=~PLLD16 ;\
	cs_temp|= PLLD8 | DIVEN ;\
	*pPMCTL = cs_temp;\
	for(cs_i=0;cs_i<16;cs_i++);\
	cs_temp&=~DIVEN;\
	cs_temp|=(INDIV | PLLBP);\
	*pPMCTL = cs_temp;\
	for(cs_i=0;cs_i<4096;cs_i++);\
	cs_temp=*pPMCTL;\
	cs_temp&=~PLLBP;\
	*pPMCTL = cs_temp;\
	for(cs_i=0;cs_i<16;cs_i++);\
	cs_temp = *pPMCTL;\
	cs_temp&=~(INDIV | PLLM63);\
	cs_temp|= (PLLM##Multiplier | INDIV##Input_Divider | PLLBP);\
	*pPMCTL = cs_temp;\
	for(cs_i=0;cs_i<4096;cs_i++);\
	cs_temp = *pPMCTL;\
	cs_temp&=~PLLBP;\
	*pPMCTL=cs_temp;\
	for(cs_i=0;cs_i<16;cs_i++);\
	cs_temp=*pPMCTL;\
	cs_temp&=~(PLLD16 | SDCKR3_5 | SDCKR4 );\
	cs_temp|= (PLLD4 | SDCKR4 | DIVEN);\
	*pPMCTL=cs_temp;\
	for(cs_i=0;cs_i<16;cs_i++);

#define ADSP_2147x_2148x_PLL_Init_INDIV_STEP_NOT_REQUIRED(Multiplier, Divider,Input_Divider, CCLK_SDCLK_ratio)\
	int cs_temp,cs_i;\
	cs_temp=*pPMCTL;\
	cs_temp&=~PLLD16 ;\
	cs_temp|= PLLD4 | DIVEN ;\
	*pPMCTL = cs_temp;\
	for(cs_i=0;cs_i<16;cs_i++);\
	cs_temp = *pPMCTL;\
	cs_temp&=~(INDIV | PLLM63);\
	cs_temp|= (PLLM##Multiplier | INDIV##Input_Divider | PLLBP);\
	*pPMCTL = cs_temp;\
	for(cs_i=0;cs_i<4096;cs_i++);\
	cs_temp = *pPMCTL;\
	cs_temp&=~PLLBP;\
	*pPMCTL=cs_temp;\
	for(cs_i=0;cs_i<16;cs_i++);\
	cs_temp=*pPMCTL;\
	cs_temp&=~(PLLD16 | SDCKR3_5 | SDCKR4 );\
	cs_temp|= (PLLD##Divider | SDCKR##CCLK_SDCLK_ratio | DIVEN);\
	*pPMCTL=cs_temp;\
	for(cs_i=0;cs_i<16;cs_i++);

#define ADSP_2147x_2148x_PLL_Init_SDCKR4_PLLN4_INDIV_STEP_NOT_REQUIRED(Multiplier, Input_Divider)\
	int cs_temp,cs_i;\
	cs_temp=*pPMCTL;\
	cs_temp&=~PLLD16 ;\
	cs_temp|= PLLD8 | DIVEN ;\
	*pPMCTL = cs_temp;\
	for(cs_i=0;cs_i<16;cs_i++);\
	cs_temp = *pPMCTL;\
	cs_temp&=~(INDIV | PLLM63);\
	cs_temp|= (PLLM##Multiplier | INDIV##Input_Divider | PLLBP);\
	*pPMCTL = cs_temp;\
	for(cs_i=0;cs_i<4096;cs_i++);\
	cs_temp = *pPMCTL;\
	cs_temp&=~PLLBP;\
	*pPMCTL=cs_temp;\
	for(cs_i=0;cs_i<16;cs_i++);\
	cs_temp=*pPMCTL;\
	cs_temp&=~(PLLD16 | SDCKR3_5 | SDCKR4 );\
	cs_temp|= (PLLD4 | SDCKR4 | DIVEN);\
	*pPMCTL=cs_temp;\
	for(cs_i=0;cs_i<16;cs_i++);

#else


#define ADSP_2147x_2148x_PLL_Init(Multiplier, Divider, Input_Divider, CCLK_SDCLK_ratio)\
	ustat1 = dm(PMCTL);\
	bit clr USTAT1  PLLD16 ;\
	bit set USTAT1  PLLD4 | DIVEN ;\
	dm(PMCTL) = ustat1;\
	lcntr=16, do first_div_delay? until lce;\
	first_div_delay?: nop;\
	bit clr ustat1 DIVEN;\
	bit set ustat1 INDIV | PLLBP;\
	dm(PMCTL) = ustat1;\
	lcntr=4096, do first_bypass_delay? until lce;\
	first_bypass_delay?:nop;\
	ustat1 = dm(PMCTL);\
	bit clr ustat1 PLLBP;\
	dm(PMCTL) = ustat1;\
	lcntr=16, do second_div_delay? until lce;\
	second_div_delay?:nop;\
	ustat1 = dm(PMCTL);\
	bit clr ustat1 INDIV | PLLM63;\
	bit set ustat1 PLLM##Multiplier | INDIV##Input_Divider | PLLBP;\
	dm(PMCTL) = ustat1;\
	lcntr=4096, do second_bypass_delay? until lce;\
	second_bypass_delay?:nop;\
	ustat1 = dm(PMCTL);\
	bit clr ustat1 PLLBP;\
	dm(PMCTL) = ustat1;\
	lcntr=16, do third_div_delay? until lce;\
	third_div_delay?:nop;\
	ustat1 = dm(PMCTL);\
	bit clr ustat1 PLLD16 | SDCKR3_5 | SDCKR4;\
	bit set ustat1 SDCKR##CCLK_SDCLK_ratio | PLLD##Divider | DIVEN;\
	dm(PMCTL) = ustat1;\
	lcntr=16, do fourth_div_delay? until lce;\
	fourth_div_delay?: nop;

#define ADSP_2147x_2148x_PLL_Init_SDCKR4_PLLN4(Multiplier, Input_Divider)\
	ustat1 = dm(PMCTL);\
	bit clr USTAT1  PLLD16 ;\
	bit set USTAT1  PLLD8 | DIVEN ;\
	dm(PMCTL) = ustat1;\
	lcntr=16, do first_div_delay? until lce;\
	first_div_delay?: nop;\
	bit clr ustat1 DIVEN;\
	bit set ustat1 INDIV | PLLBP;\
	dm(PMCTL) = ustat1;\
	lcntr=4096, do first_bypass_delay? until lce;\
	first_bypass_delay?:nop;\
	ustat1 = dm(PMCTL);\
	bit clr ustat1 PLLBP;\
	dm(PMCTL) = ustat1;\
	lcntr=16, do second_div_delay? until lce;\
	second_div_delay?:nop;\
	ustat1 = dm(PMCTL);\
	bit clr ustat1 INDIV | PLLM63;\
	bit set ustat1 PLLM##Multiplier | INDIV##Input_Divider | PLLBP;\
	dm(PMCTL) = ustat1;\
	lcntr=4096, do second_bypass_delay? until lce;\
	second_bypass_delay?:nop;\
	ustat1 = dm(PMCTL);\
	bit clr ustat1 PLLBP;\
	dm(PMCTL) = ustat1;\
	lcntr=16, do third_div_delay? until lce;\
	third_div_delay?:nop;\
	ustat1 = dm(PMCTL);\
	bit clr ustat1 PLLD16 | SDCKR3_5 | SDCKR4;\
	bit set ustat1 SDCKR4 | PLLD4 | DIVEN;\
	dm(PMCTL) = ustat1;\
	lcntr=16, do fourth_div_delay? until lce;\
	fourth_div_delay?: nop;

#define ADSP_2147x_2148x_PLL_Init_INDIV_STEP_NOT_REQUIRED(Multiplier, Divider, Input_Divider, CCLK_SDCLK_ratio)\
	ustat1 = dm(PMCTL);\
	bit clr USTAT1  PLLD16 ;\
	bit set USTAT1  PLLD4 | DIVEN ;\
	dm(PMCTL) = ustat1;\
	lcntr=16, do first_div_delay? until lce;\
	first_div_delay?: nop;\
	ustat1 = dm(PMCTL);\
	bit clr ustat1 INDIV | PLLM63;\
	bit set ustat1 PLLM##Multiplier | INDIV##Input_Divider | PLLBP;\
	dm(PMCTL) = ustat1;\
	lcntr=4096, do second_bypass_delay? until lce;\
	second_bypass_delay?:nop;\
	ustat1 = dm(PMCTL);\
	bit clr ustat1 PLLBP;\
	dm(PMCTL) = ustat1;\
	lcntr=16, do third_div_delay? until lce;\
	third_div_delay?:nop;\
	ustat1 = dm(PMCTL);\
	bit clr ustat1 PLLD16 | SDCKR3_5 | SDCKR4;\
	bit set ustat1 SDCKR##CCLK_SDCLK_ratio | PLLD##Divider | DIVEN;\
	dm(PMCTL) = ustat1;\
	lcntr=16, do fourth_div_delay? until lce;\
	fourth_div_delay?: nop;

#define ADSP_2147x_2148x_PLL_Init_SDCKR4_PLLN4_INDIV_STEP_NOT_REQUIRED(Multiplier, Input_Divider)\
	ustat1 = dm(PMCTL);\
	bit clr USTAT1  PLLD16 ;\
	bit set USTAT1  PLLD8 | DIVEN ;\
	dm(PMCTL) = ustat1;\
	lcntr=16, do first_div_delay? until lce;\
	first_div_delay?: nop;\
	ustat1 = dm(PMCTL);\
	bit clr ustat1 INDIV | PLLM63;\
	bit set ustat1 PLLM##Multiplier | INDIV##Input_Divider | PLLBP;\
	dm(PMCTL) = ustat1;\
	lcntr=4096, do second_bypass_delay? until lce;\
	second_bypass_delay?:nop;\
	ustat1 = dm(PMCTL);\
	bit clr ustat1 PLLBP;\
	dm(PMCTL) = ustat1;\
	lcntr=16, do third_div_delay? until lce;\
	third_div_delay?:nop;\
	ustat1 = dm(PMCTL);\
	bit clr ustat1 PLLD16 | SDCKR3_5 | SDCKR4;\
	bit set ustat1 SDCKR4 | PLLD4 | DIVEN;\
	dm(PMCTL) = ustat1;\
	lcntr=16, do fourth_div_delay? until lce;\
	fourth_div_delay?: nop;

#endif

/*******************************************************************************************************************************/
/*						DDR2 CONTROL INITIALIZATION															       */
/*******************************************************************************************************************************/

/*	(1)

	Description: Macro to initialize DDR2 Controller

  	Arguments:

	Parameter 			Description			  				Valid Values

    _EPCTL				External port control register		32 bit immediate value
    _DDR2CTL0			DDR2 Control register 0				32 bit immediate value
    _DDR2CTL1			DDR2 Control register 1				32 bit immediate value
    _DDR2CTL2			DDR2 Control register 2				32 bit immediate value
    _DDR2CTL3			DDR2 Control register 3				32 bit immediate value
    _DDR2CTL4			DDR2 Control register 4				32 bit immediate value
    _DDR2CTL5			DDR2 Control register 5				32 bit immediate value
    _DDR2RRC			DDR2 Refresh Rate Control register	32 bit immediate value
    _DLL_Lock_Period	DLL Lock Period						512 DDCLK cycles=Ceil(512*CCLKtoDDCLK ratio)
    _DDR2CKR			DDR2CLK: CCLK Ratio					2,3,4

*/

#ifdef _LANGUAGE_C

#define ADSP_2146x_DDR2_Init(_EPCTL, _DDR2CTL0, _DDR2CTL1, _DDR2CTL2, _DDR2CTL3, _DDR2CTL4, _DDR2CTL5, _DDR2RRC,_DLL_Lock_Period,_DDR2CKR,_DUMMY_ADD) \
		int cs_i_ddr,cs_temp_ddr;\
		*pPMCTL|= DDR2CKR##_DDR2CKR##|DIVEN;\
		for(cs_i_ddr=0;cs_i_ddr<14;cs_i_ddr++);\
		*pDLL0CTL1|=0xE00;\
		*pDLL1CTL1|=0xE00;\
		for(cs_i_ddr=0;cs_i_ddr<8;cs_i_ddr++);\
		for(cs_i_ddr=0;cs_i_ddr<##_DLL_Lock_Period##;cs_i_ddr++);\
		*pEPCTL&=0xFFFFFFF0;\
		*pEPCTL|=_EPCTL;\
		*pDDR2RRC=_DDR2RRC;\
		*pDDR2CTL1=_DDR2CTL1;\
		*pDDR2CTL2=_DDR2CTL2;\
		*pDDR2CTL3=_DDR2CTL3;\
		*pDDR2CTL4=_DDR2CTL4;\
		*pDDR2CTL5=_DDR2CTL5;\
		*pDDR2CTL0=_DDR2CTL0;\
		while((*pDDR2STAT0&DDR2DLLCALDONE)==0);

#define ADSP_2146x_DDR2_Init_DDR2CKR4(_EPCTL, _DDR2CTL0, _DDR2CTL1, _DDR2CTL2, _DDR2CTL3, _DDR2CTL4, _DDR2CTL5, _DDR2RRC,_DLL_Lock_Period,_DUMMY_ADD) \
		int cs_i_ddr,cs_temp_ddr,cs_temp_plld_original, cs_temp_plld_different;\
		cs_temp_ddr=*pPMCTL;\
		cs_temp_plld_original=(cs_temp_ddr>>6)&0x3;\
		cs_temp_plld_different=cs_temp_plld_original^0x1;\
		cs_temp_ddr&=~PLLD16;\
		cs_temp_ddr|=(cs_temp_plld_different<<6 | DIVEN);\
		*pPMCTL = cs_temp_ddr;\
	 	for(cs_i_ddr=0;cs_i_ddr<16;cs_i_ddr++);\
	 	cs_temp_ddr=*pPMCTL;\
        cs_temp_ddr&=~(PLLD16 | 0x1C0000 );\
		cs_temp_ddr|= (DDR2CKR4 | cs_temp_plld_original<<6  | DIVEN);\
 		*pPMCTL=cs_temp_ddr;\
 		for(cs_i_ddr=0;cs_i_ddr<16;cs_i_ddr++);\
		*pDLL0CTL1|=0xE00;\
		*pDLL1CTL1|=0xE00;\
		for(cs_i_ddr=0;cs_i_ddr<8;cs_i_ddr++);\
		for(cs_i_ddr=0;cs_i_ddr<##_DLL_Lock_Period##;cs_i_ddr++);\
		*pEPCTL&=0xFFFFFFF0;\
		*pEPCTL|=_EPCTL;\
		*pDDR2RRC=_DDR2RRC;\
		*pDDR2CTL1=_DDR2CTL1;\
		*pDDR2CTL2=_DDR2CTL2;\
		*pDDR2CTL3=_DDR2CTL3;\
		*pDDR2CTL4=_DDR2CTL4;\
		*pDDR2CTL5=_DDR2CTL5;\
		*pDDR2CTL0=_DDR2CTL0;\
		while((*pDDR2STAT0&DDR2DLLCALDONE)==0);


#define ADSP_2146x_DDR2_Enter_SR()\
		*pDDR2CTL0|=DDR2SRF;


#define ADSP_2146x_DDR2_Exit_SR()\
		int cs_ddr2_temp=*pDDR2CTL0;\
		cs_ddr2_temp|=BIT_25;\
		cs_ddr2_temp^=DDR2SRF;\
		*pDDR2CTL0=cs_ddr2_temp;

#define ADSP_2146x_DDR2_Enter_PD()\
		*pDDR2CTL0|=DIS_DDRCKE;


#define ADSP_2146x_DDR2_Exit_PD()\
		*pDDR2CTL0^=DIS_DDRCKE;



#else

#define ADSP_2146x_DDR2_Init(_EPCTL, _DDR2CTL0, _DDR2CTL1, _DDR2CTL2, _DDR2CTL3, _DDR2CTL4, _DDR2CTL5, _DDR2RRC,_DLL_Lock_Period,_DDR2CKR,_DUMMY_ADD) \
		ustat3=dm(PMCTL);\
		bit set ustat2 DDR2CKR##_DDR2CKR##|DIVEN;\
		dm(PMCTL)=ustat3;\
		lcntr = 14, do wait_here_ddr1? until lce;\
		wait_here_ddr1?:nop;\
		ustat3 = dm(DLL0CTL1);\
		bit set ustat3 0xE00;\
		dm(DLL0CTL1) = ustat3;\
		ustat3 = dm(DLL1CTL1);\
		bit set ustat3 0xE00;\
		dm(DLL1CTL1) = ustat3;\
		lcntr = 8, do wait_here_ddr2? until lce;\
		wait_here_ddr2?:nop;\
		lcntr=_DLL_Lock_Period;\
		do waitt until lce;\
		waitt:nop;\
		ustat3=dm(EPCTL);\
		bit clr ustat3 0xFFFFFFF0;\
		bit set ustat3 _EPCTL;\
		dm(EPCTL)=ustat3;\
		ustat3=_DDR2RRC;\
		dm(DDR2RRC)=ustat3;\
		ustat3=_DDR2CTL1;\
		dm(DDR2CTL1)=ustat3;\
		ustat3=_DDR2CTL2;\
		dm(DDR2CTL2)=ustat3;\
		ustat3=_DDR2CTL3;\
		dm(DDR2CTL3)=ustat3;\
		ustat3=_DDR2CTL4;\
		dm(DDR2CTL4)=ustat3;\
		ustat3=_DDR2CTL5;\
		dm(DDR2CTL5)=ustat3;\
		ustat3=_DDR2CTL0;\
		dm(DDR2CTL0)=ustat3;\
		wait_for_cal:USTAT3 = dm(DDR2STAT0);\
		bit tst USTAT3 DDR2DLLCALDONE;\
		if not tf jump wait_for_cal;

#define ADSP_2146x_DDR2_Init_DDR2CKR4(_EPCTL, _DDR2CTL0, _DDR2CTL1, _DDR2CTL2, _DDR2CTL3, _DDR2CTL4, _DDR2CTL5, _DDR2RRC,_DLL_Lock_Period,_DUMMY_ADD) \
		ustat3=dm(PMCTL);\
		r13=ustat3;\
		r15=PLLD16;\
		r13=r13 AND r15;\
		r14=r13 XOR r15;\
		bit clr ustat3 PLLD16;\
		r15=ustat3;\
		r15=r15 OR r14;\
		ustat3=r15;\
		bit set ustat3 DIVEN;\
		dm(PMCTL)=ustat3;\
		lcntr=16, do wait_here_ddr1? until lce;\
		wait_here_ddr1?:nop;\
		ustat3=dm(PMCTL);\
		bit clr ustat3 (PLLD16 | 0x1C0000);\
		r15=ustat3;\
		r15 = r15 or r13;\
		ustat3=r15;\
		bit set ustat3 (DDR2CKR4 | DIVEN);\
		dm(PMCTL)=ustat3;\
		lcntr=16, do wait_here_ddr2? until lce;\
		wait_here_ddr2?:nop;\
		ustat3 = dm(DLL0CTL1);\
		bit set ustat3 0xE00;\
		dm(DLL0CTL1) = ustat3;\
		ustat3 = dm(DLL1CTL1);\
		bit set ustat3 0xE00;\
		dm(DLL1CTL1) = ustat3;\
		lcntr = 8, do wait_here_ddr3? until lce;\
		wait_here_ddr3?:nop;\
		lcntr=_DLL_Lock_Period;\
		do waitt until lce;\
		waitt:nop;\
		ustat3=dm(EPCTL);\
		bit clr ustat3 0xFFFFFFF0;\
		bit set ustat3 _EPCTL;\
		dm(EPCTL)=ustat3;\
		ustat3=_DDR2RRC;\
		dm(DDR2RRC)=ustat3;\
		ustat3=_DDR2CTL1;\
		dm(DDR2CTL1)=ustat3;\
		ustat3=_DDR2CTL2;\
		dm(DDR2CTL2)=ustat3;\
		ustat3=_DDR2CTL3;\
		dm(DDR2CTL3)=ustat3;\
		ustat3=_DDR2CTL4;\
		dm(DDR2CTL4)=ustat3;\
		ustat3=_DDR2CTL5;\
		dm(DDR2CTL5)=ustat3;\
		ustat3=_DDR2CTL0;\
		dm(DDR2CTL0)=ustat3;\
		wait_for_cal:USTAT3 = dm(DDR2STAT0);\
		bit tst USTAT3 DDR2DLLCALDONE;\
		if not tf jump wait_for_cal;

#define ADSP_2146x_DDR2_Enter_SR()\
		ustat3=dm(DDR2CTL0);\
		bit set ustat3 DDR2SRF;\
		dm(DDR2CTL0)=ustat3;

#define ADSP_2146x_DDR2_Exit_SR()\
		ustat3=dm(DDR2CTL0);\
		bit clr ustat3 DDR2SRF;\
		bit set ustat3 BIT_25;\
		dm(DDR2CTL0)=ustat3;

#define ADSP_2146x_DDR2_Enter_PD()\
		ustat3=dm(DDR2CTL0);\
		bit set ustat3 DIS_DDRCKE;\
		dm(DDR2CTL0)=ustat3;

#define ADSP_2146x_DDR2_Exit_PD()\
		ustat3=dm(DDR2CTL0);\
		bit clr ustat3 DIS_DDRCKE;\
		dm(DDR2CTL0)=ustat3;

	//dm(PMCTL) = ustat3;
#endif

/*******************************************************************************************************************************/
/*						SDRAM CONTROLLER INITIALIZATION (21367/8/9, 2137x, 2147x, 2148x processors				               */
/*******************************************************************************************************************************/

/*	(1)

	Description: Macro to initialize DDR2 Controller

  	Arguments:

	Parameter 			Description			  				Valid Values

    _SYSCTL				System Control register				32 bit immediate value
    _EPCTL				External port control register		32 bit immediate value
    _SDCTL				SDRAM Control register 0			32 bit immediate value
    _SDRRC				SDRAM Refresh rate control register	32 bit immediate value
    _SDCKR				CCLK:SDRAM speed ratio				2,2_5,3,3_5,4
    _DUMMY_ADD			dummy address to initiate PSS		32 bit immediate value
*/

#ifdef _LANGUAGE_C

#define ADSP_369_2137x_2147x_2148x_SDRAM_Init(_SYSCTL, _EPCTL, _SDCTL, _SDRRC, _SDCKR,_DUMMY_ADD) \
		int cs_i_ddr,cs_temp_ddr;\
		*pPMCTL|= SDCKR##_SDCKR##|DIVEN;\
		for(cs_i_ddr=0;cs_i_ddr<14;cs_i_ddr++);\
		*pSYSCTL|=_SYSCTL;\
		*pEPCTL&=0xFFFFFFF0;\
		*pEPCTL|=_EPCTL;\
		*pSDRRC=_SDRRC;\
		cs_temp=*(volatile int*)##_DUMMY_ADD;


#define ADSP_369_2137x_2147x_2148x_SDRAM_Init_SDCKR4(_SYSCTL, _EPCTL, _SDCTL, _SDRRC, _DUMMY_ADD) \
		int cs_i_ddr,cs_temp_ddr,cs_temp_plld_original, cs_temp_plld_different;\
		cs_temp_ddr=*pPMCTL;\
		cs_temp_plld_original=(cs_temp_ddr>>6)&0x3;\
		cs_temp_plld_different=cs_temp_plld_original^0x1;\
		cs_temp_ddr&=~PLLD16;\
		cs_temp_ddr|=(cs_temp_plld_different<<6 | DIVEN);\
		*pPMCTL = cs_temp_ddr;\
		for(cs_i_ddr=0;cs_i_ddr<16;cs_i_ddr++);\
		cs_temp_ddr=*pPMCTL;\
		cs_temp_ddr&=~(PLLD16 | 0x1C0000 );\
		cs_temp_ddr|= (SDCKR4 | cs_temp_plld_original<<6  | DIVEN);\
		*pPMCTL=cs_temp_ddr;\
 		for(cs_i_ddr=0;cs_i_ddr<16;cs_i_ddr++);\
		*pSYSCTL|=_SYSCTL;\
		*pEPCTL&=0xFFFFFFF0;\
		*pEPCTL|=_EPCTL;\
		*pSDRRC=_SDRRC;\
		cs_temp=*(volatile int*)##_DUMMY_ADD;


#define ADSP_369_2137x_2147x_2148x_SDRAM_Enter_SR()\
		*pSDCTL|=SDSRF;


#define ADSP_369_2137x_2147x_2148x_SDRAM_Exit_SR()\
		int cs_sd_temp=*pSDCTL;\
		cs_sd_temp&=~SDSRF;\
		*pSDCTL=cs_sd_temp;


#else

#define ADSP_369_2137x_2147x_2148x_SDRAM_Init(_SYSCTL, _EPCTL, _SDCTL, _SDRRC, _SDCKR,_DUMMY_ADD) \
		ustat3=dm(PMCTL);\
		bit set ustat2 SDCKR##_SDCKR##|DIVEN;\
		dm(PMCTL)=ustat3;\
		lcntr = 14, do wait_here_ddr1? until lce;\
		wait_here_ddr1?:nop;\
		ustat3=dm(EPCTL);\
		bit clr ustat3 0xFFFFFFF0;\
		bit set ustat3 _EPCTL;\
		dm(EPCTL)=ustat3;\
		ustat3=_SDRRC;\
		dm(SDRRC)=ustat3;\
		ustat3=_SDCTL;\
		dm(SDCTL)=ustat3;\
		r0=dm(##_DUMMY_ADD##);

#define ADSP_369_2137x_2147x_2148x_SDRAM_Init_SDCKR4(_SYSCTL, _EPCTL, _SDCTL, _SDRRC, _DUMMY_ADD) \
		ustat3=dm(PMCTL);\
		r13=ustat3;\
		r15=PLLD16;\
		r13=r13 AND r15;\
		r14=r13 XOR r15;\
		bit clr ustat3 PLLD16;\
		r15=ustat3;\
		r15=r15 OR r14;\
		ustat3=r15;\
		bit set ustat3 DIVEN;\
		dm(PMCTL)=ustat3;\
		lcntr=16, do wait_here_ddr1? until lce;\
		wait_here_ddr1?:nop;\
		ustat3=dm(PMCTL);\
		bit clr ustat3 (PLLD16 | 0x1C0000);\
		r15=ustat3;\
		r15 = r15 or r13;\
		ustat3=r15;\
		bit set ustat3 (SDCKR4 | DIVEN);\
		dm(PMCTL)=ustat3;\
		lcntr=16, do wait_here_ddr2? until lce;\
		wait_here_ddr2?:nop;\
		ustat3=dm(EPCTL);\
		bit clr ustat3 0xFFFFFFF0;\
		bit set ustat3 _EPCTL;\
		dm(EPCTL)=ustat3;\
		ustat3=_SDRRC;\
		dm(SDRRC)=ustat3;\
		ustat3=_SDCTL;\
		dm(SDCTL)=ustat3;\
		r0=dm(##_DUMMY_ADD##);


#define ADSP_369_2137x_2147x_2148x_SDRAM_Enter_SR()\
		ustat3=dm(SDCTL);\
		bit set ustat3 SDSRF;\
		dm(SDCTL)=ustat3;


#define ADSP_369_2137x_2147x_2148x_SDRAM_Exit_SR()\
		ustat3=dm(SDCTL);\
		bit clr ustat3 SDSRF;\
		dm(SDCTL)=ustat3;

#endif


/*******************************************************************************************************************************/
/*						AMI INITIALIZATION	(21367/8/9/ and 214xx processors    										       */
/*******************************************************************************************************************************/

/*	(1)

	Description: Macro to initialize AMI

  	Arguments:

	Parameter 			Description			  				Valid Values

    _AMICTL0			AMI Control register for bank 0 					32 bit immediate value
    _AMICTL1			AMI Control register for bank 1						32 bit immediate value
    _AMICTL2			AMI Control register for bank 2						32 bit immediate value
    _AMICTL3			AMI Control register for bank 3						32 bit immediate value
*/

#ifdef _LANGUAGE_C

#define ADSP_21369_214xx_AMI_Init( _AMICTL0, _AMICTL1, _AMICTL2, _AMICTL3)\
	*pAMICTL0=_AMICTL0;\
	*pAMICTL1=_AMICTL1;\
	*pAMICTL2=_AMICTL2;\
	*pAMICTL3=_AMICTL3;


#else

#define ADSP_21369_214xx_AMI_Init( _AMICTL0, _AMICTL1, _AMICTL2, _AMICTL3)\
		ustat3=_AMICTL0;\
		dm(AMICTL0)=ustat3;\
		ustat3=_AMICTL1;\
		dm(AMICTL1)=ustat3;\
		ustat3=_AMICTL2;\
		dm(AMICTL2)=ustat3;\
		ustat3=_AMICTL3;\
		dm(AMICTL3)=ustat3;
#endif
/**********************************************************************************************************************************/





