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SETTINGS FOR BF537 EZ-KIT AND MICRON MI360 SENSOR
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EZ-KIT SWITCH/JUMPER SETTINGS:
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SW1: all off
SW2: 1=off 2=off 3=off 4=on
SW3: all off
SW4: all off
SW5: on if pushbuttons are used, off otherwise
SW6: on if flash is used, off otherwise
SW7: 1=on 2=on 3=on 4=on 5=on 6=off 7=off 8=off
SW8: 1=on 2=on 3=off 4=off 5=off 6=off

SW16 = 1 for flash boot
	
JP3.1/2
JP5.1/2
JP6 DNP
JP8 DNP
JP9 DNP
JP12 DNP

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AV-EXT POPULATED JUMPERS:
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JP1 DNP
JP2.1/2
JP3.5/7, JP3.6/8
JP4.7/8
JP5 DNP
JP6.3/5, JP6.4/6
JP7 DNP
JP8 DNP
JP9.3/5, JP9.4/6
JP10 DNP

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MI360 IMAGE FORMAT:
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Hor Pixels: 640
Ver Pixels: 480
Format: RGB
Bits per pixel: 16

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MI360 BASIC CONFIGURATION:
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Hardware:
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JPB2 DNP

Software:
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SCCB Write Address:	0xB8
SCCB Read Address:	0xB9

Note: If using BF537 TWI interface, use address 0x5C (0xB8>>1)

Reg  =  Value
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0x01 = 0x0004	// Set to Core Register Space
0x0D = 0x0001	// Soft Reset of Core
// Wait 200000 cycle delay
0x0D = 0x0000
// Wait 200000 cycle delay
0x01 = 0x0004	// Set to Core Register Space
0x05 = 0x0084	// Horizontal Blanking Control Register
0x06 = 0x0010	// Vertical Blanking Control Register
0x07 = 0x3002	// Output Control Register
0x20 = 0xD020 
0x21 = 0xE401
0x35 = 0x0040
// Wait 200000 cycle delay
0x01 = 0x0001	// Set to Image Flow Processing Space
0x07 = 0x0001
// Wait 200000 cycle delay
0x07 = 0x0000
// Wait 200000 cycle delay
0x37 = 0x0020
0x01 = 0x0001
0x05 = 0x0003	// Aperture Correction (sharpening)
0x08 = 0xDA00	// Enable RGB and invert Pixel Clock
0x2E = 0x1084	// AE  Target Control
0x3A = 0x0043	// Output Format Control 2  - 555 BGR, swap bytes
0x33 = 0x1411	// Sharpness and Saturation
0x39 = 0x0122	// Upper Shutter Delay Limit
0x3B = 0x042C	// Black Subtraction
0x3E = 0x0FFF	// Gain threshold for CCM adjustment
0x48 = 0x0007	// Color bar
0x59 = 0x00F8
0x5A = 0x012A
0x5C = 0x201E
0x5D = 0x2725
0x64 = 0x117D
// Wait 800000 cycle delay

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SAMPLE BF537 BASIC REGISTER CONFIGURATION:
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//If not using system services or ezkitutilities:

// SDRAM setup
	tempReg = *pEBIU_SDSTAT;
	tempReg = tempReg & SDRS;
		
	//SDRS is bit 8 of EBIU_SDSTAT register.
	//If SDRS (bit 8) is set (tempReg reads value 8),
	//then SDRAM registers haven't been initialized 
	//yet and needs to be configured.
	 
	if (tempReg == 8)
	{
	
		*pEBIU_SDRRC = 0x03a3;		// SDRAM Refresh Rate Control Register
		*pEBIU_SDBCTL = 0x0025;		// SDRAM Memory Bank Control Register
		*pEBIU_SDGCTL = 0x0491998d;	// SDRAM Memory Global Control Register
	}

// Port setup
	*pTIMER0_CONFIG |= 0x40;
	*pTIMER1_CONFIG |= 0x40; 
	*pTIMER2_CONFIG |= 0x40;
	
	*pPORTFIO_INEN |= 0x8380; // input enable
	*pPORTGIO_INEN |= 0x00FF;

	*pPORT_MUX &= 0xF1FF; // for use of PPI upper data byte
	*pPORT_MUX |= 0x0100; // for use of PPI_FS3
	
	*pPORTF_FER |= 0x8380; // for use of PPI_CLK and PPI_FS1,2,3
	*pPORTG_FER |= 0x000F;
	*pPORTG_FER |= 0x00F0; // for use of PPI upper data byte
	
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PART REVISIONS:
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These configurations apply to:
- BF537 Rev. 0.2 or higher
- AV-Extender card Rev. 1.2
- Micron MI360 Headboard Rev. 3
- Micron MT9v111 Sensor Rev. 3