#include <def21161.h>

.global FLASH_READ_Command;

.extern Delay_Before_Return_func;

.section/pm seg_pmco;
//PAGE READ Command
FLASH_READ_Command:
	//
	bit clr FLAGS FLG3;  //enable chip - FLASH CS# asserted here
	//Drive CLE "HI" for the command phase "A0" -> "HI" and "A1" -> "LO"
	//First byte  - command "0x00"
	r0 = 0;
	dm(0x00200001) = r0; //write to bank 3 address space - FLASH is interfaced to bank3	
	
	//Drive ALE "HI" - address phase "A1" -> "HI" and "A0" -> "LO"
	//Write "column", "row_1_2_3" address
	dm(0x00200002) = r12; //"0"th column - 0th byte
	dm(0x00200002) = r13; //"0"th row
	dm(0x00200002) = r14; 
	dm(0x00200002) = r15; 
	

	idle;//wait for Interrupt/BUSY (R/B#) signal from NAND FLASH
		
	//read data DN, DN+1......DN+527 -- "A0" -> "LO" and "A1" -> "LO"
	lcntr = 528, do page_read until lce;
	r1 = dm(0x00200000);
	page_read: dm(i0,m0) = r1;
	
	
	bit set FLAGS FLG3;//Disable chip - FLASH CS# de-asserted
	
	CALL Delay_Before_Return_func;
	
	RTS;
	FLASH_READ_Command.end:
