#include <def21161.h>

.global FLASH_PROGRAM_Command;

.extern Delay_Before_Return_func;

.section/pm seg_pmco;
//PAGE PROGRAM Command	
	FLASH_PROGRAM_Command:
	bit clr FLAGS FLG3;  //enable chip - FLASH CS# asserted here
	
	//Drive CLE "HI" for the command phase "A0" -> "HI" and "A1" -> "LO"
	//First byte  - command "0x80"
	r0 = 0x80;
	dm(0x00200001) = r0; //write to bank 3 address space - FLASH is interfaced to bank3	
	
	//Drive ALE "HI" - address phase "A1" -> "HI" and "A0" -> "LO"
	//Write "column", "rox_1_2_3" address
	
	dm(0x00200002) = r12; //"0"th column - 0th byte
	dm(0x00200002) = r13; //"0"th row 
	dm(0x00200002) = r14; //"1"st row
	dm(0x00200002) = r15; //"2"nd row
	
	//write data DN, DN+1......DN+527 -- "A1" -> "LO" and "A0" -> "LO"
	lcntr = 528, do page_write until lce;
	r1 = dm(i1,m0);
	nop;nop;nop;nop;nop;nop;nop;nop;nop;nop;nop;nop;nop;nop;nop;
	page_write: dm(0x00200000) = r1;
	
	//Give 0x10 command
	//Drive CLE "HI" -- "A0" -> "HI" and "A1" -> "LO"
	//Command "0x10"
	r0 = 0x10;
	dm(0x00200001) = r0;
	
	idle;//wait for Interrupt / BUSY (R/B#) from NAND FLASH
	bit set FLAGS FLG3;//Disable chip - FLASH CS# de-asserted
	
	CALL Delay_Before_Return_func;
	RTS;
FLASH_PROGRAM_Command.end:
