#include <def21161.h>

.global FLASH_BLOCK_Erase_Command;

.extern Delay_Before_Return_func;

.section/pm seg_dmda;
	.var Erase_Status = 0;
	
.section/pm seg_pmco;


//Block Erase Command
FLASH_BLOCK_Erase_Command:
	
	bit clr FLAGS FLG3;  //enable chip - FLASH CS# asserted here
	
	//Drive CLE "HI" for the command phase "A0" -> "HI" and "A1" -> "LO"
	//Give command "0x60"
	r0 = 0x60;
	dm(0x00200001) = r0; //write to bank 3 address space - FLASH is interfaced to bank3	

	
	//Drive ALE "HI" - address phase "A1" -> "HI" and "A0" -> "LO"

	/* For block erase, only ROW address is needed since the entire block is erased
	   with this command. Page address and element address is not used only block address
	   needs to be written.
	*/  
	dm(0x00200002) = r13; //"0"th row 
	dm(0x00200002) = r14; //"1st" row
	dm(0x00200002) = r15; //"2nd" row
	
	
	//Drive CLE "HI" for the command phase "A0" -> "HI" and "A1" -> "LO"
	
	//Give command "0xD0"
	r0 = 0xD0;
	dm(0x00200001) = r0; //write to bank 3 address space - FLASH is interfaced to bank3	
	
	
	idle; //wait for interrupt
		//Following section checks for erase status
		//--------------------------------------------------------------------
		//Drive CLE "HI" for the command phase "A0" -> "HI" and "A1" -> "LO"
		//Give command "0x70"
		r0 = 0x70;
		dm(0x00200001) = r0; //write to bank 3 address space - FLASH is interfaced to bank3	
		
		//perform read from memory "A0" and "A1" should be "LO"
		r1 = dm(0x00200000); //I/O0 should be 0 for successful erase
							 //I/O0 is "1" for erase error
		dm(Erase_Status) = r1;
		//--------------------------------------------------------------------
	
	bit set FLAGS FLG3;//Disable chip - FLASH CS# de-asserted
	
	CALL Delay_Before_Return_func;
	
	RTS;	
FLASH_BLOCK_Erase_Command.end:
