extern void Delay_Before_Return_func();


void FLASH_PROGRAM_Command(int clmn, int rw0, int rw1, int rw2, int* WrData);

extern int* FlshBankCMDptr;
extern int* FlshBankALEptr;
extern int* FlshBankWRptr;

int TmpWRData;

void FLASH_PROGRAM_Command(int clmnf, int rwf0, int rwf1, int rwf2, int* WrDataf)
{	
	int i;
	asm("#include <def21161.h>");
	asm("bit clr FLAGS FLG3;");  //enable chip - FLASH CS# asserted here
	
	//Drive CLE "HI" for the command phase "A0" -> "HI" and "A1" -> "LO"
	//First byte  - command "0x80"
	*FlshBankCMDptr = 0x80;
	
	//Drive ALE "HI" - address phase "A1" -> "HI" and "A0" -> "LO"
	//Write "column", "rox_1_2_3" address
	*FlshBankALEptr = clmnf;
	*FlshBankALEptr = rwf0;
	*FlshBankALEptr = rwf1;
	*FlshBankALEptr = rwf2;

	//write data DN, DN+1......DN+527 -- "A1" -> "LO" and "A0" -> "LO"
	for (i=0; i<=527; i++)
	{
		TmpWRData = *WrDataf;
		*FlshBankWRptr = TmpWRData;
		*WrDataf++;
	}
	
	//Give 0x10 command
	//Drive CLE "HI" -- "A0" -> "HI" and "A1" -> "LO"
	//Command "0x10"
	*FlshBankCMDptr = 0x10;
	
	asm("idle;");//wait for Interrupt / BUSY (R/B#) from NAND FLASH
	
	asm("bit set FLAGS FLG3;");//Disable chip - FLASH CS# de-asserted
	Delay_Before_Return_func();
	return;	
}

