extern void Delay_Before_Return_func();

void FLASH_READ_Command(int clmn, int rw0, int rw1, int rw2, int* RdData);

extern int* FlshBankCMDptr;
extern int* FlshBankALEptr;
extern int* FlshBankRDptr;

int RdDataTmp;

//PAGE READ Command
void FLASH_READ_Command(int clmnf, int rwf0, int rwf1, int rwf2, int* RdDataf)
{
	//
	int i;
	asm("#include <def21161.h>");
	asm("bit clr FLAGS FLG3;");  //enable chip - FLASH CS# asserted here
	//Drive CLE "HI" for the command phase "A0" -> "HI" and "A1" -> "LO"
	//First byte  - command "0x00"
	*FlshBankCMDptr = 0x00;
	
	//Drive ALE "HI" - address phase "A1" -> "HI" and "A0" -> "LO"
	//Write "column", "row_1_2_3" address
	*FlshBankALEptr = clmnf; //"0"th column - 0th byte
	*FlshBankALEptr = rwf0; //"0"th row
	*FlshBankALEptr = rwf1; 
	*FlshBankALEptr = rwf2; 
	

	asm("idle;");//wait for Interrupt/BUSY (R/B#) signal from NAND FLASH

	//read data DN, DN+1......DN+527 -- "A0" -> "LO" and "A1" -> "LO"
	for (i = 0; i<=527; i++)
	{
		RdDataTmp = *FlshBankRDptr;
		*RdDataf = (0x000000FF & RdDataTmp);
		*RdDataf++;
	}
	
	
	asm("bit set FLAGS FLG3;");//Disable chip - FLASH CS# de-asserted
	
	Delay_Before_Return_func();
	return;
}


