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This ZIP File is associated with Rev 5 of the Application Note


    Rational Sample Rate Conversion with Blackfin Processors (EE-183) 


that can be found at http://www.analog.com/ee-notes.


Date Created:	Jan 3rd, 2006


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The archive provides one code example:

The example in directory C:\SRC Rev 5 Dec 2005\src_mod illustrates a Sample Rate Converter (SRC) and Main Program Shell utilizing the ADSP-BF53x EZ-KIT Lite Evaluation Platforms. Note that if the user would like to use the other "precanned" filters (include files) please apply changes to src_xxxtoxxx.h per "IPDC comment" in the example project directory.  I leave this as an exercise to the user :-)     
										  
This C shell contains function calls and routines to initialize the state of the BF53x as well as the SRC.  This program assumes input data comes from a 16-bit buffer (initialized as 'x' in this shell).  This data is copied into a 32-bit buffer 'in1' within src_flt.asm.  At the end of src_flt.asm, the last 32-bit buffer 'inx' (where 'x' is the last stage) is copied into a 16-bit buffer ('y' in this shell).  These 16-bit input/output buffers can be eliminated to conserve data space.  In this case, you will need to undefine 'BUFIN' and preload 'in1' with 32-bit data and then use the 32-bit output data from 'inx'.
			
The converter was designed to convert between any of the following rates:
48000, 44100, 32000, 22050, 16000, 11025, and 8000.  If you have the SRC program from Momentum Data Systems (or similar) you can generate coefficients for any SRC.  Follow #3 below.  One might use workspaces within VDSP to verify all necessary plots of the input/output stages as well in the intermediate buffers.  You can look at the data in the time domain or apply the built-in FFT plotting function to analyze the frequency domain.  Load "*.vdw" from the example SRC.

I have generated a "SINE_xxxxx_16bit_1024.dat" input file to test every SRC.  This is a 16-bit, 1024-sample, 1KHz sine wave at the input sample rate.  These were generated using MATLAB (see 'gen_sine_wave_comma_16.m'). it's easy to verify proper conversion by counting samples in one period at both the input rate (in the 'x' plot) and the output rate (in the 'y' plot) in workspace #2.  Notes: 	

1. You can modify the size of NINPS and NOUTS in each 'src_xxxxtoxxxx.h' file.  However, it MUST be the	same multiple of the GCD.

2. Buffer sizes, NINPS and NOUTS must be at least half of the filter coefficient sizes times the INTPx value to ensure valid output data.

3. Do the following to convert the decimal filter coefficients from Momentum Data Systems SRC *.dsp file to properly format this data as 32-bit Hexidecimal value.  This is then read into the corresponding variable at initialization:
a. Use Excel to import the *.dsp file (space delimited).  Select the "D" column and erase everything else.  Save the file as a "Formatted Text (Space Delimited)(*.prn)" file.
b. Use the MATLATB program "dec_file_to_hex_file_converter.m".  This MATLAB program will read in floating point decimal (exponential) data from a file (*.prn) and convert to a 32-bit Hexidecimal format (*.dat file) suitable to be read by VisualDSP within a data initialization section.

4. When 'BUFIN' is undefined, the program assumes that 'in1' is preloaded with 32-bit input data AFTER the src_init is accomplished (buffer zeroing).  This requires that the shell program preload 'in1' from a 32-bit source.  Define 'BUFIN' to include the 16-bit buffer transfer code within src_flt.asm.  x and y 16-bit
buffers are nice for debug and prototyping but they do represent additional memory usage.

5. To "zero" out filter delays, use the following equations as offsets to first valid data:
1st Offset = (LENG1-1)/(2*DOWN1)
2nd Offset = INTP2/DOWN2*1st Offset + (LENG2-1)/(2*DOWN2)
3rd Offset = INTP3/DOWN3*2nd Offset + (LENG3-1)/(2*DOWN3)
See the constants generated in the 'src_xxxxtoxxxx.h' files.
					
6. DOFSx (in src_xxxxtoxxxx.h) is the offset and also is the number of valid output data samples.  This will allow you to figure how often this routine needs to be executed in a block-processed system.  Be careful with this number. The preprocessor in VDSP will not generate fractional constants.  Therefore, depending on the math here, DOFSx could have an error of +/-1.  For a particular SRC, check the first sample in 'y' and adjust the DOFSx accordingly.

7. One idea of reducing the number of intermediate buffers is to call a 'zero_buf' function that would rezero the buffers between filter sections.  This would reduce the number of intermediate buffers to two at the expense
of more MIPs.  However, the MIPs increase would be negligable and is on the order of the size of the buffer.  These two intermediate buffers should be sized to the maximum needed for any SRC.

8. If there is a big interpolation constant, this severely reduces the number of valid data samples in the final output buffer.  For example, in the 44.1K to 48K case, there is an interpolation constant of 16 in the 3rd stage. If we only use L1 data sections (max = 4096 bytes) we only get 111 valid data samples in the final output buffer.	However, if I use L2 and make this intermediate buffer as large as 4096 words (16K bytes), I can get a relatively large number of valid output data samples.  The point here is that.. depending on interpolation constants, the limiting	factor appears to be the L1 section size.  I can maximize all my filters based on this L1 section size (4096 bytes or 1024 words) ...OR..  assume someone can use L2 and make the intermediate buffers larger.  In the later case, the number of VALID	output data samples greatly increases.

9. The half band code was not implemented.  Therefore, the HALFB define is not used.

10. 11025to16, 16to2204, and 8to11025 produced corrupted data with 3-stage filters.  Had to use 2-stages.  MDS filter generator produces corrupted 3rd stage output for close sample rate conversions that required up sampling???  Not sure why.
				
11. Revision 4 of the code was debugged on a Momentum Systems Hawk PCI board.  All FileIO was done over the PCI bus.  Several things need to change in this code to work with the Hawk board:
a. Define 'HAWK'
b. Add idle.c and the basiccrt.s file for the Hawk board to the project.

12. With Rev 5, I have verified the code works on the BF533 EZKIT and on ALL existing Blackfins.  I removed the LDF from the project so this code will work "out of box" with just about any VDSP version.



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All code examples have been written and tested with

	VisualDSP++ 4.0 September Update

	ADSP-BF533 revision 0.3 silicon
	ADSP-BF535 revision 1.3 silicon
	MDS Hawk revision 1.3 
	ADSP-BF533 EZ-KIT Lite revision 1.0


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