/////////////////////////////////////////////////////////
//
//  VisualDSP++ 3.0 for Blackfin example
//
//
//  (c) Analog Devices, 
//
////////////////////////////////////////////////////////


#include "def21535.h"
#include "mydef.h"
#define N_Sour 0x4000
#define N_Dest 0x4000



.section l2_bank1;
.VAR DESTINATION1[N_Dest];  
.VAR DESTINATION2;		//[N_Dest];  

.section l2_bank1;

				    			/*	Config 	DMA		Start		Start	Next descriptor
									word 	count	AddrLo		AddrHi	pointer			
								------	------	------		-----	------			*/	
		//int enable, DMA enable, Data 32bit, set ownership
.byte2	RD_DMA_WORD_CONFIG1[6] =	0x800F, N_Sour,	0x0000, 	0x0000,		0x0000, 0; 
.byte2	RD_DMA_WORD_CONFIG2[6] =	0x8009, N_Sour,	0x0000, 	0x0000,		0x0000, 0; 
.byte2	RD_DMA_WORD_CONFIG3[6] =	0x800F, N_Sour,	0x0000, 	0x0000,		0x0000, 0; 
.byte2 	WR_DMA_WORD_CONFIG1[6] =	0x800B, N_Dest,	0x0000, 	0x0000,		0x0000, 0; 
.byte2 	WR_DMA_WORD_CONFIG2[6] =	0x800B, N_Dest,	0x0000, 	0x0000,		0x0000, 0; 
.byte2 	WR_DMA_WORD_CONFIG3[6] =	0x800B, N_Dest,	0x0000, 	0x0000,		0x0000, 0; 
.byte2 	WR_DMA_WORD_CONFIG4[6] =	0x800B, N_Dest,	0x0000, 	0x0000,		0x0000, 0; 
.byte2	DMA_END = 0;


.section data_async_bank0;
.VAR External_Source[N_Sour];

.section l2_bank0;
.global isr_application;
.global isr_dma;
.global isr_FlagA;
.global isr_FlagB;



isr_application:
_main:
	
//At first the source descriptors will be loaded with the right values
//Its two descriprors for to source DMAs chained.

	p1.l = RD_DMA_WORD_CONFIG1;
	p1.h = RD_DMA_WORD_CONFIG1;
	R0.l = External_Source;
	R0.h = External_Source;
	[p1 + 4] = r0;
	R1.l = DMA_END;			//	R1.l = RD_DMA_WORD_CONFIG2;
	w[p1 + 8] = R1;	

	p1.l = RD_DMA_WORD_CONFIG2;
	p1.h = RD_DMA_WORD_CONFIG2;
	R0.l = External_Source;
	R0.h = External_Source;
	[p1 + 4] = r0;
	R1.l = RD_DMA_WORD_CONFIG3;
	w[p1 + 8] = R1;	
	
	p1.l = RD_DMA_WORD_CONFIG3;
	p1.h = RD_DMA_WORD_CONFIG3;
	R0.l = External_Source;
	R0.h = External_Source;
	[p1 + 4] = r0;
	R1.l = DMA_END;
	w[p1 + 8] = R1;	

//At next the descriptors for the destination 

	p1.l = WR_DMA_WORD_CONFIG1;
	p1.h = WR_DMA_WORD_CONFIG1;
	R0.l = DESTINATION1;
	R0.h = DESTINATION1;
	[p1 + 4] = r0;
	R1.l = DMA_END;							//	R1.l = WR_DMA_WORD_CONFIG2;
	w[p1 + 8] = R1;	


	p1.l = WR_DMA_WORD_CONFIG2;
	p1.h = WR_DMA_WORD_CONFIG2;
	R0.l = DESTINATION2;
	R0.h = DESTINATION2;
	[p1 + 4] = r0;
	R1.l = WR_DMA_WORD_CONFIG3;
	w[p1 + 8] = R1;	

	p1.l = WR_DMA_WORD_CONFIG3;
	p1.h = WR_DMA_WORD_CONFIG3;
	R0.l = DESTINATION1;
	R0.h = DESTINATION1;
	[p1 + 4] = r0;
	R1.l = WR_DMA_WORD_CONFIG4;
	w[p1 + 8] = R1;	


	p1.l = WR_DMA_WORD_CONFIG4;
	p1.h = WR_DMA_WORD_CONFIG4;
	R0.l = DESTINATION2;
	R0.h = DESTINATION2;
	[p1 + 4] = r0;
	R1.l = DMA_END;
	w[p1 + 8] = R1;	


/**************** configure Flag Pins as interrupt **********************/
		
		
		P2.H = hi(FIO_DIR);
		P2.L = lo(FIO_DIR);
//		R0.L = 0x0000;
//		W[P2] = R0;						

		R0.L = 0xFFFF;			// mask all PF interrupts
		P2.L = lo(FIO_MASKA_C);
		w[P2] = R0;				// FIO_MASKA_C
		P2.L = lo(FIO_MASKB_C);
		w[P2] = R0;				// FIO_MASKB_C

		P2.L = lo(FIO_MASKA_S);
		R0.L = 0x0800;			// set PF11 to PF A interrupt
		w[P2] = R0;				// FIO_MASKA_S
		

		P2.L = lo(FIO_POLAR);
		R0.L = 0x0000;			// set pins polarity to high active
		w[P2] = R0;				// FIO_POLAR

		P2.L = lo(FIO_EDGE);
		R0.L = 0x0D00;			//set PF 11 and PF 10 to edge sensitive 
		w[P2] = R0;				// FIO_EDGE

		P2.L = lo(FIO_BOTH);
		R0.L = 0x0000;			// only use one edge
		w[P2] = R0;				// FIO_BOTH


/**************** Set the ASYNC Interface **********************/

	p0.h = hi(EBIU_AMBCTL0);
	p0.l = lo(EBIU_AMBCTL0);
	R0 = 0x1D17(Z);	
	W[P0] = R0;			
	SSYNC;				


	p0.h = hi(EBIU_AMGCTL);
	p0.l = lo(EBIU_AMGCTL);
	R0 = 0x0003 (z);	
	W[P0] = R0;			
	SSYNC;				

/**************** MEMDMA Startup for stand by **********************/

	R0.H=WR_DMA_WORD_CONFIG1;
	P0.L=lo(DMA_DBP);    //Descriptor Base Pointer 0xFFC0 4880
	P0.H=hi(DMA_DBP);
	W[P0] = R0.H;	//write
	
	R0.h = WR_DMA_WORD_CONFIG1;
	R0.l = WR_DMA_WORD_CONFIG1;
	P0.L=lo(MDW_DND);   // Destination Memory DMA next descriptor pointer register
	P0.H=hi(MDW_DND);
	W[P0] = R0;			// Load the address of the First Write Channel work unit 
	
	R0.h = RD_DMA_WORD_CONFIG1;
	R0.l = RD_DMA_WORD_CONFIG1;
	P0.L=lo(MDR_DND);    // Source Memory DMA next descriptor pointer register
	P0.H=hi(MDR_DND);
	W[P0] = R0;			// Load the address of the Read Channel work unit 
	


[ -- SP ] = RETI;       // enabling Interrupt nesting

	


Loop1:



	NOP;
	jump	Loop1;


.section L1_program;
	
isr_dma:

/************** INTERRUPT SERVICE ROUTINE ********************/
	[--sp]	= P4;
	[--sp] 	= R4;
	[--sp]	= R5;


	R4.l = 0x1;
	P4.l=lo(MDW_DI);
	P4.h=hi(MDW_DI);
	W[P4] = R4;			 // writing a 1 to this register clears the interrupt 	

	R4.l = 0x1;
	P4.l=lo(MDR_DI);
	P4.h=hi(MDR_DI);
	W[P4] = R4;			 // writing a 1 to this register clears the interrupt 	
	


	P4	= [sp++];
	R4	= [sp++];
	R5	= [sp++];
	rti;
	
	
/****************************************************************************************/

isr_FlagA:		// external Flag A Interrupt
		
		[--SP] = ASTAT;
		[--SP] = R0;
		[--SP] = P0;
		
		// clear interrupt request
		R0.l = 0x0800;	
		P0.H = hi(FIO_FLAG_C);
		P0.L = lo(FIO_FLAG_C);
		W[P0] = R0;						//Clear PF11
	/******************************************************/
		R0.l = 0x0400;	
		P0.H = hi(FIO_FLAG_C);
		P0.L = lo(FIO_FLAG_C);
		W[P0] = R0;						//Clear PF10

		P2.L = lo(FIO_MASKB_S);
		R0.L = 0x0400;			// set PF10 to PF B interrupt
		w[P2] = R0;				// FIO_MASKB_S


	
		P0 = [SP++];
		R0 = [SP++];
		ASTAT = [SP++];

		RTI;

/****************************************************************************************/
/****************************************************************************************/

isr_FlagB:		// external Flag B Interrupt
		
		[--SP] = ASTAT;
		[--SP] = R0;
		[--SP] = P0;
		
		// clear interrupt request
		R0.l = 0x0400;	
		P0.H = hi(FIO_FLAG_C);
		P0.L = lo(FIO_FLAG_C);
		W[P0] = R0;						//Clear PF10
	/******************************************************/

	
	
	R0=1;
	P0.l=lo(MDW_DCFG);
	P0.h=hi(MDW_DCFG);   // Configuration register enable DMA
	W[P0] = R0;	
	P0.l=lo(MDR_DCFG);
	P0.h=hi(MDR_DCFG);   // Configuration register enable DMA
	W[P0] = R0;	

	CLI R0;	
	
		P0 = [SP++];
		R0 = [SP++];
		ASTAT = [SP++];

		RTI;

/****************************************************************************************/
	