/*****************************************************************************************/
//
// Name: 	BF535 EZ-KIT Receive over external port via MEMDMA
//
/*****************************************************************************************

(C) Copyright 2003 - Analog Devices, Inc.  All rights reserved.

File Name:				Main.asm

Date Modified:			3/21/03		TL		Rev 1.2

Software:       		VisualDSP++3.1

Hardware:				BF535 EZ-KIT Board

Special Connections:  	
						

Purpose:				This project is dedicated to the Note EE-181
						Please visit Analog Devices Home page to review.


						This project initializes a descriptor based MEM DMA 
						Configures two PF pins and the async interface of the
						external port. It waits until the first PF interrupt 
						will activate the next PF interrupt. The next PF interrupt 
						will start the DMA transfer. The DMA executes an interrupt 
						after finishing and will disable all interrupt sources.

******************************************************************************************/


#include <defBF535.h>
#include "mydef.h"
#define N_Sour 0xEA60
#define N_Dest 0xEA60



.section l2_bank1;
.VAR DESTINATION1[N_Dest];  
.VAR DESTINATION2;		//[N_Dest];  

.section l2_bank0;

				    			/*	Config 	DMA		Start		Start	Next descriptor
									word 	count	AddrLo		AddrHi	pointer			
								------	------	------		-----	------			*/	
		//int enable, DMA enable, Data 32bit, set ownership
.byte2	RD_DMA_WORD_CONFIG1[6] =	0x800B, N_Sour,	0x0000, 	0x0000,		0x0000, 0; 
.byte2 	WR_DMA_WORD_CONFIG1[6] =	0x800F, N_Dest,	0x0000, 	0x0000,		0x0000, 0; 
.byte2	DMA_END = 0;


.section data_async_bank1;
.VAR External_Source[N_Sour];

.section L1_program;
.global isr_application;
.global isr_dma;
.global isr_FlagA;
.global isr_FlagB;



isr_application:
_main:
	
//At first the source descriptors will be loaded with the right values
//Its two descriprors for to source DMAs chained.

	p1.l = RD_DMA_WORD_CONFIG1;
	p1.h = RD_DMA_WORD_CONFIG1;
	R0.l = External_Source;
	R0.h = External_Source;
	[p1 + 4] = r0;
	R1.l = DMA_END;
	w[p1 + 8] = R1;	

//At next the descriptors for the destination 

	p1.l = WR_DMA_WORD_CONFIG1;
	p1.h = WR_DMA_WORD_CONFIG1;
	R0.l = DESTINATION1;
	R0.h = DESTINATION1;
	[p1 + 4] = r0;
	R1.l = DMA_END;
	w[p1 + 8] = R1;	



	
/**************** configure Flag Pins as interrupt **********************/
		
		
		P2.H = hi(FIO_DIR);
		P2.L = lo(FIO_DIR);

		R0.L = 0xFFFF;			// mask all PF interrupts
		P2.L = lo(FIO_MASKA_C);
		w[P2] = R0;				// FIO_MASKA_C
		P2.L = lo(FIO_MASKB_C);
		w[P2] = R0;				// FIO_MASKB_C

		P2.L = lo(FIO_MASKA_S);
		R0.L = 0x0800;			// set PF11 to PF A interrupt
		w[P2] = R0;				// FIO_MASKA_S
		

		P2.L = lo(FIO_POLAR);
		R0.L = 0x0000;			// set pins polarity to high active
		w[P2] = R0;				// FIO_POLAR

		P2.L = lo(FIO_EDGE);
		R0.L = 0x0D00;			//set PF 11 and PF 10 to edge sensitive 
		w[P2] = R0;				// FIO_EDGE

		P2.L = lo(FIO_BOTH);
		R0.L = 0x0000;			// only use one edge
		w[P2] = R0;				// FIO_BOTH


/**************** Set the ASYNC Interface **********************/

	p0.h = hi(EBIU_AMBCTL0);
	p0.l = lo(EBIU_AMBCTL0);
	R0.h = 0x1D17;	
	R0.l = 0x0;	
	[P0] = R0;			
	SSYNC;				


	p0.h = hi(EBIU_AMGCTL);
	p0.l = lo(EBIU_AMGCTL);
	R0 = 0x0004 (z);	
	W[P0] = R0;			
	SSYNC;				

/**************** MEMDMA Startup for stand by **********************/

	R0.H=WR_DMA_WORD_CONFIG1;
	P0.L=lo(DMA_DBP);    //Descriptor Base Pointer 0xFFC0 4880
	P0.H=hi(DMA_DBP);
	W[P0] = R0.H;	//write
	
	R0.h = WR_DMA_WORD_CONFIG1;
	R0.l = WR_DMA_WORD_CONFIG1;
	P0.L=lo(MDW_DND);   // Destination Memory DMA next descriptor pointer register
	P0.H=hi(MDW_DND);
	W[P0] = R0;			// Load the address of the First Write Channel work unit 
	
	R0.h = RD_DMA_WORD_CONFIG1;
	R0.l = RD_DMA_WORD_CONFIG1;
	P0.L=lo(MDR_DND);    // Source Memory DMA next descriptor pointer register
	P0.H=hi(MDR_DND);
	W[P0] = R0;			// Load the address of the Read Channel work unit 
	


[ -- SP ] = RETI;       // enabling Interrupt nesting

	
isr_application.END:

Loop1:



	NOP;
	jump	Loop1;


.section L1_program;
	
isr_dma:

/************** INTERRUPT SERVICE ROUTINE ********************/
	[--sp]	= P4;
	[--sp] 	= R4;
	[--sp]	= R5;


	R4.l = 0x1;
	P4.l=lo(MDW_DI);
	P4.h=hi(MDW_DI);
	W[P4] = R4;			 // writing a 1 to this register clears the interrupt 	

	R4.l = 0x1;
	P4.l=lo(MDR_DI);
	P4.h=hi(MDR_DI);
	W[P4] = R4;			 // writing a 1 to this register clears the interrupt 	

	CLI R4;

	P4	= [sp++];
	R4	= [sp++];
	R5	= [sp++];
	
isr_dma.END:	
	rti;
	
	
/****************************************************************************************/

isr_FlagA:		// external Flag A Interrupt
		
		[--SP] = ASTAT;
		[--SP] = R0;
		[--SP] = P0;
		
		// clear interrupt request
		R0.l = 0x0800;	
		P0.H = hi(FIO_FLAG_C);
		P0.L = lo(FIO_FLAG_C);
		W[P0] = R0;						//Clear PF11
	/******************************************************/
		R0.l = 0x0400;	
		P0.H = hi(FIO_FLAG_C);
		P0.L = lo(FIO_FLAG_C);
		W[P0] = R0;						//Clear PF10

		P2.L = lo(FIO_MASKB_S);
		R0.L = 0x0400;			// set PF10 to PF B interrupt
		w[P2] = R0;				// FIO_MASKB_S


	
		P0 = [SP++];
		R0 = [SP++];
		ASTAT = [SP++];

isr_FlagA.END:		
		RTI;

/****************************************************************************************/
/****************************************************************************************/

isr_FlagB:		// external Flag B Interrupt
		
		[--SP] = ASTAT;
		[--SP] = R0;
		[--SP] = P0;
		
		// clear interrupt request
		R0.l = 0x0400;	
		P0.H = hi(FIO_FLAG_C);
		P0.L = lo(FIO_FLAG_C);
		W[P0] = R0;						//Clear PF10
	/******************************************************/

	
	
	R0=1;
	P0.l=lo(MDW_DCFG);
	P0.h=hi(MDW_DCFG);   // Configuration register enable DMA
	W[P0] = R0;	
	P0.l=lo(MDR_DCFG);
	P0.h=hi(MDR_DCFG);   // Configuration register enable DMA
	W[P0] = R0;	

	
		P0 = [SP++];
		R0 = [SP++];
		ASTAT = [SP++];

isr_FlagB.END:		
		RTI;

/****************************************************************************************/
	