Интегрированный широкополосный приемник диапазона 100 МГц - 1000 МГц
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ADRF6850 - это высокоинтегрированный широкополосный квадратурный модулятор, синтезатор сетки частот и усилитель с переменным коэффициентом усиления в одном корпусе. Устройство покрывает диапазон рабочих частот от 100 МГц до 1000 МГц и может использоваться для переноса сигнала с промежуточной частоты (ПЧ) в область модулирующих частот путем квадратурной демодуляции как в узкополосных, так и в широкополосных системах связи.

Демодулятор ADRF6850 включает в себя синтезатор сетки частот с дробным коэффициентом деления и большим модулем, имеющий интегрированный ГУН и обеспечивающий разрешение по частоте менее 1 Гц, а также входной усилитель с программируемым коэффициентом усиления, обеспечивающий диапазон регулировки коэффициента усиления 60 дБ.

Управление всеми внутренними регистрами осуществляется через выбираемый пользователем интерфейс SPI или I2C. Устройство работает от одного источника питания с напряжением в диапазоне от 3.15 В до 3.45 В.

Области применения

  • Системы широкополосной связи
  • Системы сотовой связи
  • Системы спутниковой связи

Статус продукта

checked Recommended for New Designs

This product has been released to the market. The data sheet contains all final specifications and operating conditions. For new designs, ADI recommends utilization of these products.

Evaluation Kits

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Product Details

The ADRF6850 evaluation board (EVAL-ADRF6850EB1Z) is designed to allow the user to evaluate all aspects of the ADRF6850. The board comes with a software GUI on a CD which allows the user to write to the complete register set of the ADRF6850 through the parallel port of a PC either via an SPI or I2C interface. It has SMA connectors for the demodulator’s input RF signal (connected for single-ended operation on this board), the output baseband signals, the VGAIN input which controls the gain of the VGA as well as the +3.3V power supplies. It contains a 13.5 MHz reference clock for the reference input of the on-chip PLL and the ability to drive this input with an external reference clock if so desired. It contains a 4th order loop filter for the PLL which is optimized for best rms jitter performance with a 13.5 MHz reference clock and a charge pump current of 2.5 mA. The loop bandwidth is approximately 50 kHz with a phase margin of 55⁰. The PLL frequency and performance can be monitored using the LOMON outputs. These are open-collector outputs and need to be terminated to 3.3V using on-board 50 Ω resistors or pull-up inductors. Lock detect and MUXOUT can also be monitored. All supplies are decoupled by a parallel combination of 100 nF and 56 pF capacitors. Low frequency decoupling is provided by a 10 µF capacitor. More details of the evaluation board is contained in the ADRF6850 datasheet.

Tools & Simulations

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Design Tools

Design Resources

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ADI has always placed the highest emphasis on delivering products that meet the maximum levels of quality and reliability. We achieve this by incorporating quality and reliability checks in every scope of product and process design, and in the manufacturing process as well.  "Zero defects" for shipped products is always our goal.

ADRF6850 Material Declaration
PCN-PDN Information Quality And Reliability Symbols and Footprints



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The USA list pricing shown is for BUDGETARY USE ONLY, shown in United States dollars (FOB USA per unit for the stated volume), and is subject to change. International prices may differ due to local duties, taxes, fees and exchange rates. For volume-specific price or delivery quotes, please contact your local Analog Devices, Inc. sales office or authorized distributor. Pricing displayed for Evaluation Boards and Kits is based on 1-piece pricing.

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Evaluation Boards Pricing displayed is based on 1-piece.
Pricing displayed is based on 1-piece. The USA list pricing shown is for budgetary use only, shown in United States dollars (FOB USA per unit), and is subject to change. International prices may vary due to local duties, taxes, fees and exchange rates.