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The AD7780 low-noise, low-power, 24-bit sigma-delta analog-to-digital converter with integrated PGA is used in low- to mid-end weigh scale systems. The radiated immunity of the system is tested as part of the release process. This 12-page Application Note describes how to achieve the best radiated immunity performance from the AD7780, taking into account the effects of layout and component placement when designing a printed circuit board (PCB). The radiated immunity testing is performed on the complete system (ADC, PCB, and load cell) as per standard IEC 61000-4-3.
The AD7292 monitor and control IC contains all the functionality required for general-purpose monitoring of analog signals and control of external devices, including an 8‑channel multiplexer, 10-bit SAR ADC, four 10-bit DACs, a ±1°C accurate internal temperature sensor, and 12 GPIOs to aid system monitoring and control. The DAC has an output voltage range up to 5 V (LSB of 4.88 mV). The output buffer can be controlled via software or hardware. This 4-page Application Note describes the timing associated with the DAC disable function.
A digital potentiometer (digiPOT) is commonly used to set an amplifier’s gain or a regulator’s output voltage. In each case, the transfer function depends on two resistances. When a digiPOT is used to replace these resistances, the transfer function becomes logarithmic. This behavior can be desirable in some applications, such as audio, but a linear transfer function is preferred in many applications. This 4-page Application Note presents three different methods for achieving a linear output.
Simple Calibration Procedure Improves Performance of Energy Meter
This 9-page Application Note describes how to calibrate the ADE7816 energy metering IC, including equations and examples of how to calculate each constant. The ADE7816 is a high-accuracy multichannel metering IC that can measure the energy on up to six current channels. It provides a variety of energy measurements including active and reactive energy, along with rms current and voltage readings—and a variety of power quality features, including no load, reverse power, and angle measurement. The data can be accessed via SPI, I2C, or high-speed data-capture (HSDC) interfaces.
Mechanical or Hybrid Interface Controls Digital Potentiometer
Due to their high accuracy, small size, high reliability, and variety of available interfaces, digital potentiometers can provide optimal replacements for mechanical potentiometers. Applications that require rotary dial controllers can use digital potentiometers that have a digital up/down interface, which is designed to increase or decrease the linear resistance at clock rates up to 50 MHz. This interface comprises three input pins: chip select, up/down, and clock. Common mechanical potentiometer controllers, such as rotary dials or knobs, can be emulated with mechanical encoders, which typically provide three pins: ground and two out-of-phase square waves. This 2-page Application Note shows how the AD5111/AD5113/AD5115 digital potentiometers can be used with mechanical encoders and hybrid mechanical/digital interfaces.
Energy Measurement ICs Provide Advanced Metering Functions
The high cost of energy is pushing data centers and other computing businesses to find intelligent power management strategies. Their implementation requires accurate power consumption data down to the power supply level. Digital communication techniques and intelligent power supplies make the task easier, but practical challenges still exist because most power supplies are not measurement equipment. AC power monitoring is implemented in some high end systems, mainly by using dedicated ac power monitors and meters but, in most cases, only the total rack power is monitored. Because most of these systems require a power factor correction (PFC) stage, where input current and voltage have to be measured by the control loop, it is logical to consider adding power metering within the PFC controller. The ADP1047/ADP1048 digital PFC controllers offer accurate input power metering capabilities. They provide accurate measurement of input and output voltage, input current, and power. The information can be reported to a microcontroller via the PMBus interface. This 9-page Application Note shows how the ADP1047/ADP1048 can be used in advanced power meters.
It is important to provide fast, high-resolution conversions when sampling industrial signals. Previously, the highest resolution analog-to-digital converters (ADCs) available at sampling rates up to 500 kSPS were 14 bit to 18 bit. This single-supply system is optimized for sampling industrial-level signals with a 24-bit, 250 kSPS sigma- delta (Σ-Δ) ADC. Each of the two differential or four pseudo-differential channels can be scanned at a rate up to 50 kSPS with 17.2 bits of noise-free code resolution. This circuit solves the problem of acquiring and digitizing standard industrial signal levels of ±5 V, ±10 V, and 0 V to 10 V with precision low-voltage ADCs by using an innovative differential amplifier with internal laser trimmed resistors to perform the attenuation and level shifting.
This 16-bit, 100-kSPS successive-approximation analog-to-digital converter plus drive amplifier is optimized for low system power dissipation with input signals up to 1 kHz and sampling rates up to 100 kSPS. This approach, useful in battery powered or multichannel applications where power dissipation is critical, also provides benefits in applications where the ADC is idle between conversion bursts. Recommended drive amplifiers for high-performance successive-approximation ADCs typically handle a wide range of input frequencies, but applications that use a lower sampling rate can save considerable power by reducing the sampling rate and using a low-bandwidth, low-power driver. For input bandwidths up to 1 kHz and sampling rates of 100 kSPS, the AD8641 precision, low-power, JFET-input op amp offers 3‑MHz bandwidth, high signal-to-noise ratio, and low total harmonic distortion—and reduces total system power from 17.35 mW to 7.35 mW.
This 16-bit, 300-kSPS successive-approximation analog-to-digital converter plus drive amplifier is optimized for low system power dissipation with input signals up to 4 kHz and sampling rates up to 300 kSPS. This approach, useful in battery powered or multichannel applications where power dissipation is critical, also provides benefits in applications where the ADC is idle between conversion bursts. Recommended drive amplifiers for high-performance successive-approximation ADCs typically handle a wide range of input frequencies, but applications that use a lower sampling rate can save considerable power by reducing the sampling rate and using a low-bandwidth, low-power driver. For input bandwidths up to 4 kHz and sampling rates of 300 kSPS, the OP1177 precision, low-noise op amp offers 1.3 MHz bandwidth, high signal-to-noise ratio, and low total harmonic distortion—and reduces total system power from 18.75 mW to 10.75 mW.
This combined 16-bit, 6-MSPS, successive-approximation (SAR) analog-to-digital converter (ADC) and differential-to-differential driver is optimized for low noise (88.6‑dB SNR), low distortion (−110 dBc THD), and low power dissipation. The SAR architecture can sample without latency, making it ideal for high-performance multiplexed data acquisition systems, such as portable digital x-ray systems and security scanners. The 6-MSPS sampling rate allows fast sampling of multiple channels, and the ADC has true 16-bit dc linearity and a LVDS interface for low pin count and low digital noise. The fast settling time (45 ns to 0.1%) of ADA4897-1 makes it ideal for multiplexed applications.
This circuit uses the ADuCM360 precision analog microcontroller in an accurate thermocouple temperature monitoring application to controls the 4-mA to 20-mA output current. The ADuCM360 integrates two 24-bit sigma-delta (Σ-Δ) analog-to-digital converters, two programmable current sources, a 12-bit digital-to-analog converter, a 1.2-V reference, an ARM Cortex-M3 core, 126 KB flash, 8 kB SRAM, and various digital peripherals, such as UART, timers, SPIs, and I2C interfaces. In the circuit, the ADuCM360 connects to a Type T thermocouple and a 100-Ω platinum resistance temperature detector, which is used for cold junction compensation. The low-power Cortex-M3 core converts the ADC readings to a real temperature value. The −200°C to +350°C Type T temperature range is converted to an output current range of 4 mA to 20 mA. The loop powered circuit operates with loop voltages up to 28 V to provide a complete solution for thermocouple measurements.
This circuit uses the ADuC7060 or the ADuC7061 precision analog microcontroller in an accurate thermocouple temperature monitoring application. The microcontrollers integrate dual 24-bit sigma-delta (Σ-Δ) analog-to-digital converters (ADCs), dual programmable current sources, a 14-bit digital-to-analog converter (DAC), and a 1.2 V internal reference—as well as an ARM7 core, 32 KB flash, 4 KB SRAM, UART, timers, serial peripheral interface (SPI), I2C interfaces, and various other digital peripherals. The ADuC7060/ ADuC7061 are connected to a thermocouple and a 100-Ω platinum resistance temperature detector (RTD), which is used for cold-junction compensation. As an extra option, the ADT7311 digital temperature sensor can measure the cold-junction temperature instead of the RTD.
This band-pass receiver front-end is based on the ADL5565 ultralow-noise differential amplifier driver and the AD9642 14-bit, 250-MSPS analog-to-digital converter (ADC). The third-order Butterworth antialiasing filter is optimized based on the performance and interface requirements of the amplifier and ADC. The total insertion loss due to the filter network and other components is only 5.8 dB. The overall circuit has a bandwidth of 18 MHz with a pass-band flatness of 3 dB. With a 127-MHz analog input, it features 71.7-dBFS signal-to-noise ratio (SNR) and 92-dBc spurious-free dynamic range (SFDR). The sampling frequency is 205 MSPS, thereby positioning the IF input signal in the second Nyquist zone between 102.5 MHz and 205 MHz.
This circuit uses the AD5700, the industry’s lowest power and smallest footprint HART®1-compliant IC modem, and the AD5422 16-bit current output and voltage output DAC to form a complete HART-compatible 4-mA to 20-mA solution. An OP184 op amp allows the IOUT and VOUT pins to be shorted together, thus reducing the number of screw connections required in programmable logic control (PLC) module applications. For additional space savings, the AD5700-1 offers a 0.5% precision internal oscillator.
This circuit is a complete thermocouple signal-conditioning circuit with cold-junction compensation followed by a 16-bit sigma-delta (Σ-Δ) analog-to-digital converter (ADC). The AD8495 thermocouple amplifier provides a simple, low-cost solution for measuring K-type thermocouple temperatures, including cold-junction compensation. Its fixed-gain instrumentation amplifier scales the small thermocouple voltage to provide a 5 mV/°C output. The amplifier’s high common-mode rejection blocks common-mode noise picked up by the long thermocouple leads. For additional protection, its high-impedance inputs make it easy to add extra filtering. The AD8476 differential amplifier provides the correct signal levels and common-mode voltage to drive the AD7790 16-bit, Σ-Δ ADC, providing a compact, low-cost solution for thermocouple signal conditioning and high-resolution analog-to-digital conversion.
This circuit uses the
AD5700 modem and the
AD5420 16-bit current-output
DAC to form a complete HART-compatible 4-mA to 20-mA solution that adheres
to HART physical layer specifications including analog rate of change and
noise during silence. For many years, 4-mA to 20-mA communication has been
used in process-control instrumentation because it is reliable, robust,
and insensitive to environmental interference over long communication
distances, but, it only allows one-way communication of one process
variable at a time. The highway addressable remote transducer (HART)
standard overcomes this limitation, providing two-way digital
communication along with 4‑mA to 20‑mA analog signaling used by
traditional instrumentation equipment, and enabling remote calibration,
fault interrogation, and transmission of additional process variables.
HART communications modulates a 1-mA peak-to-peak frequency-shift-keyed
(FSK) signal on top of the
This complete, smart, industrial loop-powered field instrument has a 4-mA to 20-mA analog output and a highway addressable remote transducer (HART®) interface. HART is a digital 2-way communication in which a 1 mA peak-to-peak frequency-shift-keyed (FSK) signal is modulated on top of the standard 4-mA to 20-mA analog current signal. This allows features such as remote calibration, fault interrogation, and transmission of process variables in applications such as temperature and pressure control.
Dual 10-bit nanoDAC Digital-to-Analog Converters include 2-ppm/°C reference
The AD5313R and AD5338R dual, 10-bit nanoDAC® buffered voltage-output DACs include an internal 2.5-V, 2-ppm/°C reference that is enabled by default. A gain-select pin sets the full-scale output to 2.5 V or 5 V. Guaranteed monotonic by design, the DACs exhibit less than 0.1% FSR gain error and 1.5-mV offset error. A power-on reset circuit ensures that the outputs power up to zero scale or midscale and remain at that level until a valid write takes place. The AD5313R includes an SPI-compatible serial interface that operates at clock rates up to 50 MHz and supports readback and daisy-chaining in systems with higher channel counts; the AD5338R includes an SPI-compatible serial interface that operates at clock rates up to 400 kHz. Operating on a 2.7-V to 5.5-V supply, the devices are compatible with 1.8-V to 5.5-V logic. They draw 1.1 mA when the internal reference is on and 0.59 mA when it is off. A per-channel power-down mode reduces the supply current to 1 µA. Specified from –40°C to +105°C, the AD5313R/38R are available in 16-lead TSSOP and 3-mm × 3-mm LFCSP packages, and are priced at $1.96 in 1000s.
14-bit, 32-channel DAC with programmable full-scale output-voltage of 50 V to 200 V
AD5535B denseDAC® high-voltage
D/A converter integrates 32
14-bit DACs and 32 high-voltage amplifiers. Its full-scale output voltage
range can be programmed from 50 V to 200 V by changing the reference from 1
V to 4 V, making it ideal for deflection and control of mirrors in optical
MEMS (micro-electromechanical systems)—and for use in optical crosspoint
switches, micropositioning applications using piezoelectric actuators, and
automotive level-setting applications. Data is written to the selected DAC
register via a 3-wire SPI-compatible interface that operates at clock rates
up to 30 MHz. Guaranteed monotonic, the DACs have 550-μA drive capability.
An on-chip thermal diode facilitates temperature monitoring. The AD5535B
operates with a ±4.75-V to ±5.25-V analog supply, 2.7-V to 5.25-V digital
supply, and 215-V high-voltage supply. Specified from –10°C to 85°C, it is
available in a
Quad, 12-/16-bit nanoDAC+ Digital-to-Analog Converters
AD5687/AD5689 dual, 12-/16-bit nanoDAC+TM
buffered voltage-output DACs feature ±1-/±2-LSB max INL, 0.1% max gain
Dual, 12-/16-bit nanoDAC+ Digital-to-Analog Converters include 2-ppm/°C reference
AD5687R/AD5689R dual, 12-/16-bit nanoDAC+TM
buffered voltage-output DACs include an internal 2.5-V, 2-ppm/°C reference
that is enabled by default. A gain-select pin sets the full-scale output to
2.5 V or 5 V, and a power-on
reset circuit ensures that the outputs power up to zero scale or midscale
and remain at that level until a valid write takes place. Guaranteed
monotonic by design, the DACs feature ±1-/±2-LSB max INL, 0.1% max gain
error, and 1.5-mV max offset error. The SPI-compatible serial interface,
which operates at clock rates up to 50 MHz, supports readback and
daisy-chaining in systems with higher channel counts. Operating on a 2.7-V
to 5.5-V supply, the devices are compatible with 1.8-V to 5.5-V logic. They
draw 1.1 mA in normal mode and 1 µA in power-down mode.
Specified from –40°C to +105°C, the AD5687R/89R are available in 16-lead
Dual, 12-bit nanoDAC+ Digital-to-Analog Converter includes 2-ppm/°C reference
The AD5697R dual, 12-bit nanoDAC+TM
buffered voltage-output DAC includes an internal 2.5-V, 2-ppm/°C reference
that is enabled by default. A gain-select pin sets the full-scale output to
2.5 V or 5 V, and a power-on
reset circuit ensures that the output powers up to zero scale or midscale
and remains at that level until a valid write takes place. Guaranteed
monotonic by design, the DACs features ±1-LSB max INL, 0.1% max gain error,
and 1.5-mV max offset error. The I2C-compatible serial interface
operates at clock rates up to 400 kHz. Operating on a 2.7-V to 5.5-V supply
and compatible with 1.8-V to 5.5-V logic, the AD5697R draws 1.1 mA in
normal mode and 1 µA in power-down mode. Specified from –40°C to
+105°C, it is available in 16-lead TSSOP and
Low-power 14-bit, 180-MSPS Digital-to-Analog Converter and Waveform Generator
The AD9102 TxDAC® digital-to-analog converter combines a high-performance DAC with on-chip pattern memory for complex waveform generation using a direct digital synthesizer (DDS). The DDS generates a 14-bit sine wave at up to 180 MHz for use as a master clock. A 24-bit tuning word enables 10.8-Hz frequency resolution; an SRAM can store waveforms, modulation patterns, and DDS tuning words; and a state machine programs the period and start delay within the period. Control and configuration data is loaded via an SPI-compatible interface. Operating on a single 1.8-V supply, the AD9102 dissipates 51 mW at 180 MSPS and 1.49 mW in power-down mode. Available in a 32‑lead LFCSP package, it is specified from –40°C to +85°C and priced at $12.35 in 1000s.
11-/14-bit, 5.6-GSPS RF Digital-to-Analog Converters
The AD9119/AD9129 high performance 11-/14-bit RF digital-to-analog converters support data rates up to 2.8 GSPS. The quad-switch architecture enables dual-edge clocking, effectively increasing the DAC update rate to 5.6 GSPS when configured for Mix-Mode™ or 2× interpolation. Baseband mode supports up to 158 contiguous carriers for CATV infrastructure applications. Mix-Mode operation can reconstruct RF carriers in the second and third Nyquist zones while maintaining exceptional dynamic range up to 4.2 GHz. The DAC output current can be programmed over the 9.5 mA to 34.4 mA range. The dual-port, synchronous LVDS port simplifies the data interface to a host FPGA/ASIC. An SPI-compatible serial port is used for configuration and monitoring. Operating on +1.8-V and –1.5-V supplies, the AD9119/29 dissipate 1 W in normal mode and 23.4 mW in reduced-power mode. Available in 160-ball CSP-BGA packages, they are specified from –40°C to +85°C and priced from $49.00 in 1000s.
The AD9106 TxDAC® digital-to-analog converter combines a high-performance quad DAC with on-chip pattern memory for complex waveform generation using a direct digital synthesizer (DDS). The DDS generates 12-bit sine waves at up to 180 MHz for use as a master clock. A 24-bit tuning word enables 10.8-Hz frequency resolution. Four independently phased programmable sine waves at a single output frequency are provided to the four DACs—with each furnishing independently adjustable gain and offset. An SRAM can store waveforms, modulation patterns, and DDS tuning words; and a state machine programs the period for all four DACs and the start delay within the period for each DAC. Control and configuration data is loaded via an SPI-compatible interface. Operating on a single 1.8-V supply, the AD9106 dissipates 167 mW at 180 MSPS and 1.49 mW in power-down mode. Available in a 32‑lead LFCSP package, it is specified from –40°C to +85°C and priced at $15.00 in 1000s.
Anthony Desimone, Michael Giancioppo, Grasp the Critical Issues for a Functioning JESD204B Interface, EE Times, 2013-04-19
Ian Beavers, Synchronizing Multiple ADCs using JESD204B, EE World, 2013-04-09
Maithil Pachchigar, Complete Sensor-to-Bits Solution Simplifies Industrial Data-Acquisition System Design, Analog Dialogue, 2013-04-01
Jonathan Harris, The ABCs of Interleaved ADCs, EDN, 2013-02-17
Umesh Jayamohan, Understand How Amplifier Noise Contributes to Total Noise in ADC Signal Chains, Analog Dialogue, 2013-02-04
David Buchanan, Resolution vs. ENOB, Analog Dialogue, 2013-02-04
David Kress, Data Converters Exert Analog Influence In A Digital World, Electronic Design, 2012-12-17
Ian Beavers, Synchronizing Multiple ADCs using JESD204B, ED China, 2012-12-13
Daniel Fague and Sara Nadeau, RF DACs simplify power and space in downstream cable transmitter systems, EDN, 2012-12-15
Alan Walsh, Front-End Amplifier and RC Filter Design for a Precision SAR Analog-to-Digital Converter, Analog Dialogue, 2012-12-03
David Buchanan, Apples and Oranges, Analog Dialogue, 2012-11-05
Tracey Johnson, HART Communication Networks Are Improved by Small, Flexible, Low-Power Modem ICs, Analog Dialogue, 2012-10-03
Gil Engel, Dan Fague and Assaf Toledano, RF Digital-to-Analog Converters Enable Direct Synthesis of Communications Signals, IEEE Communications, 2012-10-01
Shane O'Meara, Making Batteries Last Longer with Fast, High-Precision SAR Analog-to-Digital Converters, Analog Dialogue, 2012-09-04
Shane O'Meara, Low power system design optimizations with SAR A/D converters, EE Times Europe, 2012-09-01
Steven Xie, Karl Wei, Claire Croke, ADuC7026 Provides Programmable Voltages for Evaluating Multiple Power Supply Systems, Analog Dialogue, 2012-08-01
John Ardizzoni, Driving Miss ADC, Analog Dialogue, 2012-08-01
Solving the Elusive Baseband to Antenna Problem using RFDAC Technology - This webinar will explore RF transmitter architectures, concentrating on the direct-to-RF architecture enabled by RFDAC technology. Aspects of the direct-to-RF transmitter system design will be explored including gain, signal bandwidth, digital signal processing requirements, frequency planning, thermal noise, clock synthesis + phase noise, harmonics, sampling images, pre-distortion techniques, and deterministic latency.
Fundamentals of Data Conversion in Receivers - This webinar examines a contemporary receive signal chain and takes a close look at selecting suitable data converters, their key specifications, and the tradeoffs that must be made.
Fundamentals of Energy Metering - This webinar will explore system architectures for 3‑phase electricity meters, focusing on various current sensors and considerations for the analog front end, power supply and data isolation, metrology computations and system performance. Current transformers (CTs), di/dt (Rogowski coils), and shunt resistors will be discussed.
How to Lower Power Consumption in Data Acquisition Systems -- This webcast will present solutions to lower the power consumption in data-acquisition systems. Among the topics to be discussed are the limitations and tradeoffs of using lower power components, such as ADC drivers and regulators. If you are currently in the design phase of a lower power data-acquisition system, this is a webcast you should attend.
Fundamentals of Designing with Analog to Digital Converters -- Back by popular demand: an update to The Fundamentals of the Analog to Digital Converter (ADC) webcast, including basic ADC architectures, understanding ADC errors, how to read an ADC data sheet, and how to choose the right ADC. Includes the latest information about ADC products and technology.
Fundamentals of Designing with Digital to Analog Converters - BACK BY POPULAR DEMAND: An update to The Fundamentals of the Digital to Analog Converter (DAC) webcast, including basic DAC architectures, understanding DAC errors, how to read a DAC data sheet, how to choose the right DAC. Includes the latest on DAC technology.
Demystifying the JESD204B High-speed Data Converter-to-FPGA interface - This webcast will provide an overview of the JESD204 standard from its original version up to the current "B" revision. In addition, common "high-performance metrics" that are associated with high-speed serial interfaces such as JESD204 will be described. Topics covered in this webcast will also be useful for applications that use similar high-speed serial interfaces.
The Latest on Driving ADCs Differentially: Part 2 - The second of a 2-part series addressing how to select the right differential ADC driver for your design, this webinar takes the basic concepts presented in part 1 and uses them to select the driver and design driving circuits.
The Latest on Driving ADCs Differentially: Part 1 - The first of a 2-part series addressing how to select the right differential ADC driver for your design, this webinar looks at the basics of driving ADCs, including errors in sampled data systems, such as distortion and noise; ENOB; differential signaling definitions and advantages; and ADC driver architectures.
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