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Application Notes

AN-1304: ADE7912/ADE7913 DC Measurement Performance

The ADE7912 and ADE7913 isolated 3-channel, Σ-Δ ADCs target polyphase energy metering applications using shunt current sensors. The devices can be used to sense dc signals, however, so this 5-page Application Note presents their dc measurement performance. In energy metering applications, the current channel is used to sense the voltage across shunt current sensors and the voltage channels are used to measure voltages across resistor dividers. From a dc measurement perspective, this separation is not meaningful because every channel can be used to sense dc signals. This application note describes the performance when dc signals are applied at the inputs of the three Σ-Δ ADCs.

AN-1296: Optimizing Power Supplies for the AD9129

The evaluation board for the AD9129 14-bit, 5.6-GSPS RF digital-to-analog converter uses power supply filters to guarantee optimal performance. This 3-page Application Note explores the effects of removing most of the filter components. All ferrite beads on the board were removed, as well as the majority of the capacitors on the power supplies. Phase noise, noise spectral density (NSD), spurious-free dynamic range (SFDR), intermodulation distortion (IMD), and adjacent channel leakage ratio (ACLR) performance were all measured to demonstrate the effect of removing the filter components. The measurement results showed that the ferrite beads improved close-in phase noise at 20 Hz offset by approximately 5 dB, as well as single-tone IMD by up to 5 dB. Most of the capacitors proved to be redundant, however. The decoupling capacitors improved the ACLR for 6 MHz carriers by 5 dB; and the capacitor arrays improved the ACLR for 6 MHz carriers by approximately 6 dB and the NSD by approximately 1 dB. Removing all of the other the capacitors did not affect the performance.

AN-1291: Digital Potentiometers: Frequently Asked Questions

This 18-page Application Note answers a series of frequently asked questions about digital potentiometer (digiPOT) products. It includes general questions as well as specific questions, including product-specific questions. In addition, it provides digiPOT configuration information.

AN-1289: Using the AD5755 and Similar Dynamic Power Control DACs in Applications Without Dynamic Power Control

This 7-page Application Note describes using the AD5755 and other similar industrial DACs in applications that do not require the dynamic power control (DPC) feature. DPC operates by sensing the load on the current output pin and supplying only the power that is required. To achieve this, the DAC controls a dc-to-dc converter to step up a 5-V supply to between 7.4 V and 29.5 V. DPC is particularly useful in systems with wide load ranges, including a short-circuit to ground, where all power generated by the supply is dissipated on chip. In non-DPC systems, this results in higher IC and system temperatures. Low-power applications may not require dynamic power control. In these cases, the dc-to-dc converter can be excluded from the design, reducing the number of external components. This is useful for space-constrained applications that require four channels. Instead of using the dc-to-dc converter, an external PMOS can limit on-chip power dissipation, or the DAC can be powered directly, with all power dissipated on chip.

AN-1279: How to Oversample 5 MSPS, 18-Bit/16-Bit Precision SAR Converters to Increase Dynamic Range

High-performance data acquisition signal chains used for spectroscopy, magnetic resonance imaging (MRI), and gas chromatography—and vibration, oil/gas, and seismic systems demand a state-of-the-art, high dynamic range (DR) while addressing difficult thermal design, space, and cost challenges. One way to achieve a higher dynamic range is to oversample the converter to accurately monitor and measure both small and large input signals from the sensors. Other ways include using programmable-gain amplifiers or operating multiple ADCs in parallel, using digital postprocessing to average the result. These methods may be cumbersome or impractical to implement in some systems, mainly due to power, space, and cost constraints. This 4-page Application Note focuses on the oversampling of high-throughput, 5‑MSPS, 18-bit/16-bit precision successive approximation register (SAR) converters by implementing a straightforward averaging of ADC output samples to increase the dynamic range.

Circuits from the Lab

CN-0350: 12-bit, 1-MSPS, Single-Supply, Two-Chip Data-Acquisition System for Piezoelectric Sensors

This 12-bit, 1-MSPS data-acquisition system uses only two active devices. The system processes charge input signals from piezoelectric sensors using a single 3.3-V supply and has a total error of less than 0.25% FSR after calibration over a ±10°C temperature range, making it ideal for a wide variety of laboratory and industrial measurements. The circuit’s small footprint makes this combination an industry-leading solution for data-acquisition systems where accuracy, speed, cost, and size play a critical role.

CN0348: 16-Bit Single-Supply Buffered Voltage Output Digital-to Analog Conversion with Less Than ±1 LSB Integral and Differential Nonlinearity

This complete single-supply,16-bit buffered voltage output DAC maintains ±1 LSB integral and differential nonlinearity by utilizing a CMOS DAC followed by an innovative amplifier that has no crossover distortion. The circuit eliminates the crossover nonlinearity associated with most rail-to-rail op amps that can be as high as 4 LSBs to 5 LSBs in a 16-bit system. This industry leading solution is ideal for industrial process control and instrumentation applications that require a compact, single-supply, low-cost, highly linear 16-bit buffered voltage source. Total power dissipation for the three active devices is less than 25 mW typical when operating on a single 6-V supply.

CN0337: 12-Bit, 300 kSPS, Single-Supply, Fully Isolated RTD Temperature Measurement System with 3-Wire Compensation

This completely isolated 12-bit, 300-kSPS RTD temperature measuring system uses only three active devices to process the output of a Pt100 RTD. An innovative circuit provides lead-wire compensation using a standard 3-wire connection. The circuit operates on a single 3.3-V supply. The total error after room temperature calibration is less than ±0.24% FSR for a ±10°C change in temperature, making it ideal for a wide variety of industrial temperature measurements. Both data and power are isolated, making the circuit robust to high voltages and ground-loop interference often encountered in harsh industrial environments.

CN0336: 12-Bit, 300 kSPS, Single-Supply, Fully Isolated, Data Acquisition System for 4-20 mA Inputs

This completely isolated 12-bit, 300-kSPS data-acquisition system uses only three active devices to process 4-mA to 20-mA input signals using a single 3.3-V supply. The total error after room temperature calibration is ±0.06% FSR over a ±10°C temperature range, making it ideal for a wide variety of industrial measurements. The small footprint makes it an industry-leading solution for 4-mA to 20-mA data acquisition systems where accuracy, speed, cost, and size play a critical role. Both data and power are isolated, making the circuit robust to high voltages and ground-loop interference often encountered in harsh industrial environments.

CN0335: 12-Bit, 300 kSPS, Single-Supply, Fully Isolated, Data Acquisition System for ±10 V Inputs

This completely isolated 12-bit, 300-kSPS data acquisition system uses only three active devices to process ±10-V input signals using a single 3.3-V supply. The total error after room temperature calibration is less than ±0.1% FSR over a ±10°C temperature change, making it ideal for a wide variety of industrial measurements. Both data and power are isolated, thereby making the circuit robust to high voltages and ground-loop interference often encountered in harsh industrial environments.

CN0321: Fully Isolated, Single Channel Voltage and 4 mA to 20 mA Output with HART

This complete, fully isolated, analog output channel is suitable for programmable logic controllers (PLCs) and distributed control system (DCS) modules that require standard 4 mA to 20 mA HART®-compatible current outputs and unipolar or bipolar output voltage ranges. It provides a flexible building block for channel-to-channel isolated PLC/DCS output modules or any other industrial application that requires a fully isolated analog output. The circuit also includes external protection on the analog output terminals. The AD5422 16-bit digital-to-analog converter (DAC) is software configurable and provides all the necessary current and voltage outputs. The AD5700-1 HART-compliant modem, used in conjunction with the AD5422, forms a complete HART-compatible 4 mA to 20 mA solution. The AD5700-1 includes a precision internal oscillator that provides additional space savings, especially in channel-to-channel isolated applications.

New Product Briefs

July 2014

Dual 16-bit, 310-MSPS pipelined ADC provides LVDS outputs

ad9652The AD9652 dual, 16-bit analog-to-digital converter samples at up to 310 MSPS. Designed to support high-speed signal-processing applications that require high dynamic range over a wide input frequency range, its –157.6-dBFS noise floor and 85 dBFS spurious-free dynamic range (SFDR) allow low-level signals to be resolved in the presence of large signals. The dual ADC cores feature a multistage, pipelined architecture with integrated output error correction logic. The high-performance on-chip voltage reference and buffer minimize external circuitry. The ADC can support input clock frequencies of up to 1.24 GHz, with a 1×, 2×, 4×, or 8× clock divider generating the ADC sample clock. A duty cycle stabilizer compensates for variations in the ADC clock duty cycle. The two16-bit ADC outputs are interleaved onto a single LVDS output port along with a double-data-rate (DDR) clock. Programming for setup and control are accomplished via a 3-wire SPI-compatible serial interface. Operating on 1.8-V and 3.3-V supplies, the AD9652 dissipates 2.2 W in normal mode, 80 mW in standby mode, and 1 mW in power-down mode. Available in a 144-ball CSP-BGA package, it is specified from –40°C to +85°C and priced at $231.25 in 1000s.

Analog Front-End for radar receive path includes ADC, 4-channel LNA/PGA/AAF

ad8285The AD8285 analog front-end for radar receive paths includes four channels of low-noise amplifier (LNA), programmable-gain amplifier (PGA), and antialiasing filter (AAF), plus a direct-to-ADC channel, a 5-channel multiplexer, and a 12-bit ADC. Each channel has a 16-dB to 34-dB gain range in 6-dB increments; and the ADC converts at up to 72 MSPS. The combined input referred noise voltage of the entire channel is 3.5 nV/√Hz at maximum gain. Designed for low cost, low power, compact size, flexibility, and ease of use, the device is optimized for dynamic performance and low power in applications where a small package size is critical. Operating on 1.8-V and 3.3-V supplies, the AD8285 dissipates 185 mW in normal mode and 5 mW in power-down mode. Available in a 72-lead power LFCSP package, it is specified from –40°C to +105°C and priced at $8.33 in 1000s.

June 2014

Isolated 16-bit Sigma-Delta Modulator

ad7403The AD7403 high-performance, second-order, Σ-Δ modulator converts an analog input into a high-speed, single-bit data stream, with on-chip digital isolation based on iCoupler technology. Operating from a 5-V supply, it accepts a ±250 mV (±320 mV full-scale) differential input signal, making it ideally suited to monitor shunt voltages in high-voltage applications that require galvanic isolation. The analog input is continuously sampled and converted to a bit stream at up to 20 MHz. The original signal can be reconstructed with a digital filter to achieve 88-dB signal-to-noise ratio (SNR) at 78.1 kSPS. The serial interface, which operates at 3 V or 5 V, provides 5-kV rms isolation and 25-kV/µs common-mode transient immunity. Available in a 16-lead SOIC package, the AD7403 is specified from –40°C to +125°C and priced at $3.35 in 1000s.

12-bit, 2.0-GSPS Pipelined ADC

ad9625The AD9625 sampling analog-to-digital converter achieves 12-bit performance at conversion rates of up to 2.0 GSPS. Designed for sampling wide bandwidth analog signals up through the 2nd Nyquist zone, its combination of wide input bandwidth, high sampling rate, and excellent linearity is ideally suited for spectrum analyzers, data acquisition systems, and a wide assortment of military electronics applications, such as radar and electronic countermeasures (ECM). The JESD204B-based high-speed serialized outputs are configurable in a variety of one-, two-, four-, six-, or eight-lane arrangements. Operating on a 1.3-V and 2.5-V supplies, the AD9625 dissipates 3.5 W. Available in a 196-ball BG_ED package, it is specified from –40°C to +85°C and priced at $625.00 in 1000s.

Dual 14-bit, 1-GSPS Pipelined ADC

ad9680The AD9680 dual 14-bit, 1 GSPS analog-to-digital converter includes an on-chip buffer and sample-and-hold circuit, making it small, low power, and easy to use. Designed for sampling wide bandwidth analog signals of up to 2 GHz, it is optimized for wide input bandwidth, high sampling rate, excellent linearity, and low power in a small package. The dual ADC cores use a multistage, differential pipelined architecture with integrated output error correction logic. An on-chip voltage reference eases design considerations. Each ADC output is connected to a digital down converter, which consists of a 12-bit NCO, a half-band decimating filter, an FIR filter, a gain stage, and a complex-real conversion stage. The JESD204B-based high-speed serialized outputs are configurable in a variety of one-, two-, or four-lane alternatives. Configuration is accomplished via a 3-wire SPI-compatible interface. Flexible power-down options allow significant power savings. Operating on 1.25-V, 1.8-V, 2.5-V, and 3.3-V supplies, the AD9680 dissipates 3.3 W in normal mode, 1.4 W in standby mode, and 835 mW in power-down mode. Available in a 64-lead LFCSP package, it is specified from –40°C to +85°C and priced at $584.38 in 1000s.

Mixed-Signal Front-End (MxFE®)

ad9993The AD9993 mixed-signal front-end integrates four 14-bit ADCs and two 14-bit DACs. The high-speed DACs and multistage pipelined ADCs are designed to be used in wide bandwidth communication systems. The datapaths include FIFO buffers to absorb phase differences between LVDS lane clocks and the data converter sampling clocks. The devices is programmable via the SPI-compatible interface. Operating on 1.8-V and 3.3-V supplies, the AD9993 dissipates 1.5 W with a single-tone input and single-tone output and 33 mW in power-down mode. Available in a 196-ball CSP-BGA package, it is specified from –40°C to +85°C and priced at $148.70 in 1000s.

Technical Articles

Del Jones, JESD204B Subclasses (part 2): Subclass 1 vs. 2, System Considerations, EDN, 2014-06-25

Del Jones, JESD204B Subclasses (part 1): Intro and Deterministic Latency, EDN, 2014-06-18

Duncan Bosworth, Demand for digital: Challenges and solutions for high-speed ADCs and RADAR systems, EDN, 2014-06-11

David Buchanan, Overranged Converter Recovers Quickly, Analog Dialogue, 2014-06-04

David Buchanan, Overranged Converter Recovers Quickly, Planet Analog, 2014-06-04

Jonathan Harris, ADC Power Supplies: Inputs, Planet Analog, 2014-06-02

Vicky Wong, Zero-crossover-distortion amplifiers improve linearity of DAC Systems, Power Systems Design, 2014-06-01

Rob Reeder, GSPS Converter Wideband Front-End Design, DigiKey, 2014-05-28

Ian Beavers, Understanding Spurious-Free Dynamic Range In Wideband GSPS ADCs, Electronic Design, 2014-05-12

Jonathan Harris, ADC Noise: The Clock Input and Phase Noise, Part 3 – Test Setup, Planet Analog, 2014-04-18

Jim Scarlett, Capacitance-to-Digital Converter Facilitates Level Sensing in Diagnostic Systems, Analog Dialogue, 2014-04-02

Jarrett Liner, Understanding and designing wideband output networks for high speed D/A converters, EDN, 2014-03-19

Ian Beavers and Jeff Ugalde, Selecting the Right Converter: JESD204B vs. LVDS, Xilinx EE Trend, 2014-03-20

Jakub Szymczak, Shane O’Meara, Johnny S. Gealon, and Christopher Nelson De La Rama, Precision Resolver-to-Digital Converter Measures Angular Position and Velocity, Analog Dialogue, 2014-03-03

David Buchanan, Programmable ADC Input Range Provides System Benefits, Analog Dialogue, 2014-03-03

Jonathan Harris, ADC Noise: The Clock Input & Phase Noise (Jitter), Part 2, Planet Analog, 2014-02-27

Ian Beavers, Demystifying Deterministic Latency Within JESD204B Converters, Electronic Design, 2014-02-25

Jonathan Harris, ADC Noise: The Clock Input & Phase Noise (Jitter), Part 1, Planet Analog, 2014-02-18

Gabriele Manganaro, A 12 mW Low Power Continuous-Time Bandpass ΔΣ Modulator With 58 dB SNDR and 24 MHz Bandwidth at 200 MHz IF, JSSC, 2014-02-01

Rob Reeder, Designing for Wideband RF, EDN, 2014-01-28

Rob Reeder, Design Wideband Front Ends for GSPS Converters, Electronic Design, 2014-01-24

Jonathan Harris, ADC Noise: How the Clock Input Can Help, Planet Analog, 2014-01-24

Ian Beavers, Prototyping Systems: JESD204B Converters And FPGAs, Electronic Design, 2014-01-23

Ian Beavers and Jeff Ugalde, Selecting the Right Converter: JESD204B vs. LVDS, Xcell Journal, 2014-01-17

Jonathan Harris, ADC Noise: More on the Analog Inputs, Planet Analog, 2014-01-14

Jonathan Harris, How Do You Analyze ADC Noise? Part 2, Planet Analog, 2013-12-27

Jonathan Harris, How Do You Analyze ADC Noise? Part 1, Planet Analog, 2013-12-26

Maithil Pachchigar, Let's Compare SAR & Δ-Σ Converters for a Mux'd DAS, Part 5, Planet Analog, 2013-12-17

Maithil Pachchigar, Let's Compare SAR & Δ-Σ Converters for a Mux'd DAS, Part 4, Planet Analog, 2013-12-13

Maithil Pachchigar, Let's Compare SAR & Δ-Σ Converters for a Mux'd DAS, Part 3, Planet Analog, 2013-12-12

Jonathan Harris, ADC Power Supply Noise: PSRR & PSMR, Planet Analog, 2013-12-12

Jonathan Harris and Ian Beavers, Why There's No Need to Fear JESD204B, EE Times, 2013-12-11

Maithil Pachchigar, Let's Compare SAR & Δ-Σ Converters for a Mux'd DAS, Part 2 , Planet Analog, 2013-12-11

Maithil Pachchigar, Let's Compare SAR & Δ-Σ Converters for a Mux'd DAS, Part 1 , Planet Analog, 2013-12-10

Maithil Pachchigar and Richard Liggiero, Get ADC data beyond the datasheet, EDN, 2013-12-10

Jonathan Harris, Further into the alphabet with interleaved ADCs, EDN, 2013-12-02

Steven Xie, Successive-Approximation ADCs: Ensuring a Valid First Conversion, Analog Dialogue, 2013-12-02

Maithil Pachchigar, Increase Dynamic Range With SAR ADCs Using Oversampling, Part 2, Planet Analog, 2013-11-22

Maithil Pachchigar, Increase Dynamic Range With SAR ADCs Using Oversampling, Part 1, Planet Analog, 2013-11-21

Jonathan Harris, ADC Noise: A Second Look, Part 2, Planet Analog, 2013-11-15

Jonathan Harris, ADC Noise: A Second Look, Part 1, Planet Analog, 2013-11-14

David Buchanan, Overrange Flag Indicates Data Validity, Analog Dialogue, 2013-11-01

Jonathan Harris, ADC Noise – Where Does It Come From?, Planet Analog, 2013-10-21

Maithil Pachchigar, Data acquisition system enhances images for digital X-Ray and MRI, New Electronics, 2013-10-08

Jonathan Harris, Interleaving Spurs: The Mathematics of Timing Mismatch, Planet Analog, 2013-10-07

Ian Beavers, Pair The Right JESD204B Converter With Your FPGA, Electronic Design, 2013-10-03

Maithil Pachchigar, High-Performance Data-Acquisition System Enhances Images for Digital X-Ray and MRI, Analog Dialogue, 2013-10-01

Jonathan Harris, Interleaving Spurs: More Math Details for Gain Mismatch, Planet Analog, 2013-09-25

Jonathan Harris, Interleaving Spurs: Let’s Look at the Math, Planet Analog, 2013-09-17

Jonathan Harris, Understanding JESD204B Link Parameters, Planet Analog, 2013-09-10

Jonathan Harris, Interleaving Spurs: Bandwidth Mismatches, Planet Analog, 2013-08-29

Yi Zhang and Assaf Toledano, High-Speed DACs Fuel Multiband Transmitters, Microwaves & RF, 2013-08-22

Jonathan Harris, Interleaving Spurs: Timing Mismatches, Planet Analog, 2013-08-21

Alan Walsh, The Mystery of SAR ADC Power Specifications, Planet Analog, 2013-08-14

Rob Reeder, Noise considerations in high-speed converter signal chains, DSP-FPGA, 2013-08-07

David Buchanan, Soft Clipping vs. Hard Clipping, Analog Dialogue, 2013-08-04

Ian Beavers, Synchronize Multiple ADCs with JESD204B, Electronic Design, 2013-07-29

Jonathan Harris, Interleaving Spurs: Gain Mismatches, Planet Analog, 2013-07-26

Jonathan Harris, Interleaving Spurs: Offset Mismatches, Planet Analog, 2013-07-11

Ian Beavers, Slay Your System Dragons with JESD204B, Electronic Design, 2013-06-26

Jonathan Harris, More Thoughts on Interleaved ADCs, Planet Analog, 2013-06-26

Jonathan Harris, Link synchronization and alignment in JESD204B: Understanding control characters, EE Times, 2013-06-19

Alan Walsh, Voltage Reference Design for Precision Successive-Approximation ADCs, Analog Dialogue, 2013-06-03

Webinars and Tutorials

Designing Wideband Front-ends for GSPS Converters - As high-speed A/D converter technology improves, so does the need to resolve very high intermediate frequencies (IF) accurately at high-speeds. This poses two challenges: the converter design itself, and the front-end design that couples the signal content to the converter. This webcast will define wideband passive networks and highlight important specifications for choosing a transformer or balun.

Solving the Elusive Baseband to Antenna Problem using RFDAC Technology - This webinar will explore RF transmitter architectures, concentrating on the direct-to-RF architecture enabled by RFDAC technology. Aspects of the direct-to-RF transmitter system design will be explored including gain, signal bandwidth, digital signal processing requirements, frequency planning, thermal noise, clock synthesis + phase noise, harmonics, sampling images, pre-distortion techniques, and deterministic latency.

Fundamentals of Data Conversion in Receivers - This webinar examines a contemporary receive signal chain and takes a close look at selecting suitable data converters, their key specifications, and the tradeoffs that must be made.

Fundamentals of Energy Metering - This webinar will explore system architectures for 3‑phase electricity meters, focusing on various current sensors and considerations for the analog front end, power supply and data isolation, metrology computations and system performance. Current transformers (CTs), di/dt (Rogowski coils), and shunt resistors will be discussed.

How to Lower Power Consumption in Data Acquisition Systems -- This webcast will present solutions to lower the power consumption in data-acquisition systems. Among the topics to be discussed are the limitations and tradeoffs of using lower power components, such as ADC drivers and regulators. If you are currently in the design phase of a lower power data-acquisition system, this is a webcast you should attend.

Fundamentals of Designing with Analog to Digital Converters -- Back by popular demand: an update to The Fundamentals of the Analog to Digital Converter (ADC) webcast, including basic ADC architectures, understanding ADC errors, how to read an ADC data sheet, and how to choose the right ADC. Includes the latest information about ADC products and technology.

Fundamentals of Designing with Digital to Analog Converters - BACK BY POPULAR DEMAND: An update to The Fundamentals of the Digital to Analog Converter (DAC) webcast, including basic DAC architectures, understanding DAC errors, how to read a DAC data sheet, how to choose the right DAC. Includes the latest on DAC technology.

Demystifying the JESD204B High-speed Data Converter-to-FPGA interface - This webcast will provide an overview of the JESD204 standard from its original version up to the current "B" revision. In addition, common "high-performance metrics" that are associated with high-speed serial interfaces such as JESD204 will be described. Topics covered in this webcast will also be useful for applications that use similar high-speed serial interfaces.

 

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