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High-performance data acquisition signal chains used for spectroscopy, magnetic resonance imaging (MRI), and gas chromatography—and vibration, oil/gas, and seismic systems demand a state-of-the-art, high dynamic range (DR) while addressing difficult thermal design, space, and cost challenges. One way to achieve a higher dynamic range is to oversample the converter to accurately monitor and measure both small and large input signals from the sensors. Other ways include using programmable-gain amplifiers or operating multiple ADCs in parallel, using digital postprocessing to average the result. These methods may be cumbersome or impractical to implement in some systems, mainly due to power, space, and cost constraints. This 4-page Application Note focuses on the oversampling of high-throughput, 5‑MSPS, 18-bit/16-bit precision successive approximation register (SAR) converters by implementing a straightforward averaging of ADC output samples to increase the dynamic range.
This circuit provides unipolar and bipolar data conversion using the AD5754BREZ quad 16-bit, serial input, unipolar/bipolar voltage output DAC and the REF192ESZ precision 2.5 V voltage reference. The only additional external components needed are decoupling capacitors on the supply pins and reference input, leading to savings in cost and board space. This circuit is well suited for closed-loop servo control applications.
This circuit provides unipolar and bipolar digital-to-analog conversion using the AD5754R quad 16-bit, serial input, unipolar/bipolar voltage output DAC. The only external components needed are decoupling capacitors on the supply pins and reference input, leading to savings in cost and board space. This circuit is well suited for closed-loop servo control applications.
This circuit provides unipolar/bipolar voltage and 4 mA-to-20 mA outputs using the AD5422 single channel, 16-bit, serial input, unipolar/bipolar voltage and 4 mA-to-20 mA current source DAC. The only external components needed are decoupling capacitors on the supply pins and reference input and a pull-up resistor for the open-drain FAULT output, which alerts to a loss of compliance voltage on the current output or an overtemperature condition. This solution offers a level of integration that leads to savings in both cost and board space, making it well suited for programmable logic controllers and distributed control systems in industrial control applications.
This complete single-supply,16-bit buffered voltage output DAC maintains ±1 LSB integral and differential nonlinearity by utilizing a CMOS DAC followed by an innovative amplifier that has no crossover distortion. The circuit eliminates the crossover nonlinearity associated with most rail-to-rail op amps that can be as high as 4 LSBs to 5 LSBs in a 16-bit system. This industry leading solution is ideal for industrial process control and instrumentation applications that require a compact, single-supply, low-cost, highly linear 16-bit buffered voltage source. Total power dissipation for the three active devices is less than 25 mW typical when operating on a single 6-V supply.
This completely isolated 12-bit, 300-kSPS data-acquisition system uses only three active devices to process 4-mA to 20-mA input signals using a single 3.3-V supply. The total error after room temperature calibration is ±0.06% FSR over a ±10°C temperature range, making it ideal for a wide variety of industrial measurements. The small footprint makes it an industry-leading solution for 4-mA to 20-mA data acquisition systems where accuracy, speed, cost, and size play a critical role. Both data and power are isolated, making the circuit robust to high voltages and ground-loop interference often encountered in harsh industrial environments.
This complete, fully isolated, analog output channel is suitable for programmable logic controllers (PLCs) and distributed control system (DCS) modules that require standard 4 mA to 20 mA HART®-compatible current outputs and unipolar or bipolar output voltage ranges. It provides a flexible building block for channel-to-channel isolated PLC/DCS output modules or any other industrial application that requires a fully isolated analog output. The circuit also includes external protection on the analog output terminals. The AD5422 16-bit digital-to-analog converter (DAC) is software configurable and provides all the necessary current and voltage outputs. The AD5700-1 HART-compliant modem, used in conjunction with the AD5422, forms a complete HART-compatible 4 mA to 20 mA solution. The AD5700-1 includes a precision internal oscillator that provides additional space savings, especially in channel-to-channel isolated applications.
This circuit provides a low cost solution to temperature monitoring because most of the circuit functionality is integrated into the ADuCM360 precision analog microcontroller, including dual 24-bit Σ-Δ ADCs, the ARM Cortex™-M3 processor core, and the PWM/DAC features for controlling the 4 mA-to-20 mA loop for loop voltages up to 28 V.
This 16-bit, ultra-stable, low-noise, precision, bipolar (±10 V) voltage source requires a minimum number of precision external components. It features ±0.5 LSB maximum integral nonlinearity (INL) and differential nonlinearity (DNL) with the AD5760 voltage-output DAC (B-grade). The complete system has less than 0.1-LSB p-p noise and drift measured over a 100-second interval. The circuit is ideal for medical instrumentation, test and measurement, and industrial control applications where precision low drift voltage sources are required.
This circuit uses the ADuCM360 precision analog microcontroller in an accurate thermocouple temperature monitoring application and controls the 4-mA to 20-mA output current. The ADuCM360 integrates two 24-bit sigma-delta (Σ-Δ) analog-to-digital converters (ADCs), two programmable current sources, a 12-bit digital-to-analog converter (DAC), and a 1.2 V internal reference, as well as an ARM Cortex-M3 core, 126 kB flash, 8 kB SRAM, and various digital peripherals, such as UART, timers, SPIs, and I2C interfaces. The ADuCM360 is connected to a type-T thermocouple and a 100-Ω platinum resistance temperature detector, which is used for cold junction compensation. The low power Cortex-M3 core converts the ADC readings to a real temperature value. The −200°C to +350°C type-T temperature range is converted to a 4-mA to 20-mA output current. The loop-powered circuit provides a complete solution for thermocouple measurements with a minimum requirement for external components.
Ultralow-power, 2-/4-/8-channel, 12-bit, 1-MSPS successive-approximation ADCs
The AD7091R-2, AD7091R-4, and AD7091R-8 ultralow-power multichannel successive-approximation analog-to-digital converters achieve 12-bit accuracy at 1-MSPS sampling rates while consuming only 1.4 mW. Available with two, four, or eight analog input channels, the devices include a wide bandwidth track-and-hold amplifier that can handle input frequencies in excess of 1.5 MHz, a conversion clock, an accurate 2.5-V reference, a high-speed SPI-compatible serial interface, and a channel sequencer that allows a preprogrammed selection of channels to be converted sequentially. MUXOUT and ADCIN pins allow signal conditioning of the multiplexer output prior to acquisition by the ADC. Specified with a 2.7-V to 5.25-V supply, the devices are compatible with 1.8-V to 5.5-V logic. Operating on a single 3‑V supply, they consume 1.4 mW at 1 MSPS, 70 µW in static mode, and 1.4 µW in power-down mode. Available in 16-/20-/24-leadTSSOP packages, the AD7091R-2/-4/-8 are specified from –40°C to +125°C and priced at $2.47/$2.67/$3.36 in 1000s.
6-channel, 16-bit, 250-ksps, simultaneous-sampling Successive-Approximation ADCs
The AD7656A and AD7656A-1 six-channel, 16-bit, 250-ksps successive-approximation ADCs combine six high-speed, low-power ADCs and six wideband, low-noise track-and-hold amplifiers in a single package. Three convert-start inputs allow independent simultaneous sampling of three ADC pairs. The device accepts true bipolar inputs with selectable full-scale ranges of ±5 V or ±10 V, and provides both serial and parallel outputs. The successive-approximation architecture ensures that there will be no pipeline delays. Specifications include 85.5-dB signal-to-noise-plus-distortion (SINAD), –92-dB total harmonic distortion (THD), ±1-LSB integral nonlinearity (INL), and no missing codes. The AD7656A-1 requires fewer decoupling capacitors than the AD7656A, offering a lower bill of materials cost. Operating on 5-V and ±15-V supplies, the devices consume 140 mW in normal mode and 100 µW in power-down mode. Available in a 64-lead LQFP packages, they are specified from –40ºC to 85ºC and priced at $12.45 in 1000s.
18-bit, 100-/500-kSPS successive-approximation ADCs
successive-approximation ADCs achieve 18-bit resolution with no missing
10-bit nanoDAC Digital-to-Analog Converters include 2-ppm/°C reference
The AD5310R and AD5311R 10-bit nanoDAC® buffered voltage-output DACs include an internal 2.5-V, 2-ppm/°C reference that is enabled by default. A gain-select pin sets the full-scale output to 2.5 V or 5 V. Guaranteed monotonic by design, the DACs exhibit less than 0.06% FSR gain error and 1.5-mV offset error. A power-on reset circuit ensures that the outputs power up to zero scale and remain at that level until a valid write takes place. The AD5310R includes an SPI-compatible serial interface that operates at clock rates up to 50 MHz and supports readback and daisy-chaining in systems with higher channel counts; the AD5311R includes an I2C-compatible serial interface that operates at clock rates up to 400 kHz. Operating on a 2.7-V to 5.5-V supply, the devices are compatible with 1.8-V to 5.5-V logic. They draw 350 µA when the internal reference is on and 110 µA when it is off. A per-channel power-down mode reduces the supply current to 2 µA. Specified from –40°C to +105°C, the AD5310R/11R are available in 10-lead MSOP packages and are priced at $1.29 in 1000s.
12-/14-/16-bit nanoDAC Digital-to-Analog Converters include 2-ppm/°C reference
AD5681R/AD5682R/AD5683R 12-/14-/16-bit nanoDAC®
buffered voltage-output DACs include an internal
16-bit nanoDAC Digital-to-Analog Converter
AD5683 16-bit nanoDAC® buffered
voltage-output DAC operates with an external voltage reference. A
gain-select pin sets the full-scale output to VREF or 2 × VREF.
Guaranteed monotonic by design, the DAC exhibits less than 0.06% FSR gain
error and 1.5-mV offset error. A power-on reset circuit ensures that the
output powers up to zero scale and remains at that level until a valid write
takes place. The SPI-compatible serial interface operates at clock rates up
to 50 MHz and supports readback and daisy-chaining in systems with higher
channel counts. Operating on a 2.7-V to 5.5-V supply, the DAC is compatible
with 1.8-V to 5.5-V logic, drawing 350 µA when the internal reference is
on, 110 µA when it is off, and 2 µA in power-down mode.
Specified from –40°C to +105°C, the AD5683 is available in a 2-mm ×
High-performance 12-channel, 24-bit, 192-kHz Differential-Output DACs
The ADAU1962 high-performance digital audio circuit comprises 12 multibit Σ-Δ DACs with differential outputs, plus digital filters and volume controls. The DACs provide 118-dB dynamic range and –98-dB total harmonic distortion plus noise (THD+N). A microcontroller can adjust volume and other parameters, and read the temperature of the on-chip temperature sensor, via an SPI/I2C port. For low EMI, the on-chip PLL derives the master clock from an external left/right frame clock—eliminating the need for a separate high-frequency master clock and allowing the DACs to be used with or without a bit clock. The continuous-time architecture and low-voltage operation combine to further minimize EMI, power consumption, and digital waveform amplitudes. The ADAU1962 uses two separate power sources or a single analog supply with an on-chip regulator producing the digital supply. Operating with a 4.5-V to 5.5-V analog supply, 2.25-V to 3.6-V digital supply, and a 3.0-V to 5.5-V logic supply, it consume 421 mW in normal mode and 15 µW in power-down mode. Available in an 80-lead LQFP package, it is specified from –40°C to +105°C, release to automotive (RTA) qualified, and priced at $5.52 in 1000s.
Dual 16-bit, 1-MSPS Successive-Approximation ADC accepts differential inputs
The AD7903 dual 16-bit, PulSAR® analog-to-digital converter includes two low-power, high-speed, sampling ADCs and a versatile serial interface. Sampling at up to 1 MSPS, it achieves ±0.5-LSB integral nonlinearity (INL), ±0.4-LSB differential nonlinearity (DNL), 93.5-dB signal-to-noise-and-distortion (SINAD), –112-dB total-harmonic distortion (THD), and no missing codes. It accepts differential inputs in the ±VREF range, where the externally applied VREF can vary between 2.4 V and 5.1 V. The SPI-compatible serial interface allows daisy chaining of multiple ADCs and provides an optional busy indicator. Operating on a single 2.5-V supply, the device dissipates 12 mW at 1 MSPS, 40 µW at 10 kSPS, and 1 nW in standby mode. A separate I/O supply provides compatibility with 1.8-V to 5.5‑V logic. Available in a 20‑lead QSOP package, the AD7903 is specified from –40°C to +125°C and priced at $15.00 in 1000s.
Quad 16-bit, 125-MSPS Pipelined ADC provides JESD204B outputs
AD9656 quad, 16-bit, 125-MSPS pipelined
analog-to-digital converter includes four high-speed, low-power ADCs,
versatile serial and JESD204B interfaces, and a buffered voltage reference.
Sampling at up to 125 MSPS, it achieves
Dual 16-bit, 1600-MSPS TxDAC+ Digital-to-Analog Converter
AD9142A dual 16-bit, 1600-MSPS TxDAC+®
digital-to-analog converter enables multicarrier signal generation at
frequencies up to Nyquist. Optimized for direct-conversion transmit
applications, it includes complex digital modulation; input signal power
detection; and gain, phase, and offset compensation. The 2×/4×/8×
interpolator/complex modulator enables carrier placement anywhere within the
DAC bandwidth. The DAC outputs interface seamlessly with quadrature
modulators in the ADL537x
Jonathan Harris, ADC Noise: The Clock Input & Phase Noise (Jitter), Part 1, Planet Analog, 2014-02-18
Gabriele Manganaro, A 12 mW Low Power Continuous-Time Bandpass ΔΣ Modulator With 58 dB SNDR and 24 MHz Bandwidth at 200 MHz IF, JSSC, 2014-02-01
Rob Reeder, Designing for Wideband RF, EDN, 2014-01-28
Rob Reeder, Design Wideband Front Ends for GSPS Converters, Electronic Design, 2014-01-24
Jonathan Harris, ADC Noise: How the Clock Input Can Help, Planet Analog, 2014-01-24
Ian Beavers, Prototyping Systems: JESD204B Converters And FPGAs, Electronic Design, 2014-01-23
Ian Beavers and Jeff Ugalde, Selecting the Right Converter: JESD204B vs. LVDS, Xcell Journal, 2014-01-17
Jonathan Harris, ADC Noise: More on the Analog Inputs, Planet Analog, 2014-01-14
Jonathan Harris, How Do You Analyze ADC Noise? Part 2, Planet Analog, 2013-12-27
Jonathan Harris, How Do You Analyze ADC Noise? Part 1, Planet Analog, 2013-12-26
Maithil Pachchigar, Let's Compare SAR & Δ-Σ Converters for a Mux'd DAS, Part 5, Planet Analog, 2013-12-17
Maithil Pachchigar, Let's Compare SAR & Δ-Σ Converters for a Mux'd DAS, Part 4, Planet Analog, 2013-12-13
Maithil Pachchigar, Let's Compare SAR & Δ-Σ Converters for a Mux'd DAS, Part 3, Planet Analog, 2013-12-12
Jonathan Harris, ADC Power Supply Noise: PSRR & PSMR, Planet Analog, 2013-12-12
Jonathan Harris and Ian Beavers, Why There's No Need to Fear JESD204B, EE Times, 2013-12-11
Maithil Pachchigar, Let's Compare SAR & Δ-Σ Converters for a Mux'd DAS, Part 2 , Planet Analog, 2013-12-11
Maithil Pachchigar, Let's Compare SAR & Δ-Σ Converters for a Mux'd DAS, Part 1 , Planet Analog, 2013-12-10
Maithil Pachchigar and Richard Liggiero, Get ADC data beyond the datasheet, EDN, 2013-12-10
Jonathan Harris, Further into the alphabet with interleaved ADCs, EDN, 2013-12-02
Steven Xie, Successive-Approximation ADCs: Ensuring a Valid First Conversion, Analog Dialogue, 2013-12-02
Maithil Pachchigar, Increase Dynamic Range With SAR ADCs Using Oversampling, Part 2, Planet Analog, 2013-11-22
Maithil Pachchigar, Increase Dynamic Range With SAR ADCs Using Oversampling, Part 1, Planet Analog, 2013-11-21
Jonathan Harris, ADC Noise: A Second Look, Part 2, Planet Analog, 2013-11-15
Jonathan Harris, ADC Noise: A Second Look, Part 1, Planet Analog, 2013-11-14
David Buchanan, Overrange Flag Indicates Data Validity, Analog Dialogue, 2013-11-01
Jonathan Harris, ADC Noise – Where Does It Come From?, Planet Analog, 2013-10-21
Maithil Pachchigar, Data acquisition system enhances images for digital X-Ray and MRI, New Electronics, 2013-10-08
Jonathan Harris, Interleaving Spurs: The Mathematics of Timing Mismatch, Planet Analog, 2013-10-07
Ian Beavers, Pair The Right JESD204B Converter With Your FPGA, Electronic Design, 2013-10-03
Maithil Pachchigar, High-Performance Data-Acquisition System Enhances Images for Digital X-Ray and MRI, Analog Dialogue, 2013-10-01
Jonathan Harris, Interleaving Spurs: More Math Details for Gain Mismatch, Planet Analog, 2013-09-25
Jonathan Harris, Interleaving Spurs: Let’s Look at the Math, Planet Analog, 2013-09-17
Jonathan Harris, Understanding JESD204B Link Parameters, Planet Analog, 2013-09-10
Jonathan Harris, Interleaving Spurs: Bandwidth Mismatches, Planet Analog, 2013-08-29
Yi Zhang and Assaf Toledano, High-Speed DACs Fuel Multiband Transmitters, Microwaves & RF, 2013-08-22
Jonathan Harris, Interleaving Spurs: Timing Mismatches, Planet Analog, 2013-08-21
Alan Walsh, The Mystery of SAR ADC Power Specifications, Planet Analog, 2013-08-14
Rob Reeder, Noise considerations in high-speed converter signal chains, DSP-FPGA, 2013-08-07
David Buchanan, Soft Clipping vs. Hard Clipping, Analog Dialogue, 2013-08-04
Ian Beavers, Synchronize Multiple ADCs with JESD204B, Electronic Design, 2013-07-29
Jonathan Harris, Interleaving Spurs: Gain Mismatches, Planet Analog, 2013-07-26
Jonathan Harris, Interleaving Spurs: Offset Mismatches, Planet Analog, 2013-07-11
Ian Beavers, Slay Your System Dragons with JESD204B, Electronic Design, 2013-06-26
Jonathan Harris, More Thoughts on Interleaved ADCs, Planet Analog, 2013-06-26
Jonathan Harris, Link synchronization and alignment in JESD204B: Understanding control characters, EE Times, 2013-06-19
Alan Walsh, Voltage Reference Design for Precision Successive-Approximation ADCs, Analog Dialogue, 2013-06-03
Jonathan Harris, Interleaved ADCs: The Basics, Planet Analog, 2013-05-29
Maithil Pachchigar, Sensor-To-Bits: Simplifying DAQ Design, Electronic Specifier, 2013-05-20
Ian Beavers and Jeff Ugalde, Channel compensation methods used in JESD204B converters, EE Times, 2013-05-09
Jonathan Harris, LVDS Is Dead? Long Live LVDS & JESD204B, Planet Analog, 2013-05-07
Umesh Jayamohan, Understanding How Amplifier Noise Contributes to Total Noise in ADC Signal Chains, TechOnline India, 2013-04-30
Anthony Desimone, Michael Giancioppo, Grasp the Critical Issues for a Functioning JESD204B Interface, EE Times, 2013-04-19
Ian Beavers, Synchronizing Multiple ADCs using JESD204B, EE World, 2013-04-09
Solving the Elusive Baseband to Antenna Problem using RFDAC Technology - This webinar will explore RF transmitter architectures, concentrating on the direct-to-RF architecture enabled by RFDAC technology. Aspects of the direct-to-RF transmitter system design will be explored including gain, signal bandwidth, digital signal processing requirements, frequency planning, thermal noise, clock synthesis + phase noise, harmonics, sampling images, pre-distortion techniques, and deterministic latency.
Fundamentals of Data Conversion in Receivers - This webinar examines a contemporary receive signal chain and takes a close look at selecting suitable data converters, their key specifications, and the tradeoffs that must be made.
Fundamentals of Energy Metering - This webinar will explore system architectures for 3‑phase electricity meters, focusing on various current sensors and considerations for the analog front end, power supply and data isolation, metrology computations and system performance. Current transformers (CTs), di/dt (Rogowski coils), and shunt resistors will be discussed.
How to Lower Power Consumption in Data Acquisition Systems -- This webcast will present solutions to lower the power consumption in data-acquisition systems. Among the topics to be discussed are the limitations and tradeoffs of using lower power components, such as ADC drivers and regulators. If you are currently in the design phase of a lower power data-acquisition system, this is a webcast you should attend.
Fundamentals of Designing with Analog to Digital Converters -- Back by popular demand: an update to The Fundamentals of the Analog to Digital Converter (ADC) webcast, including basic ADC architectures, understanding ADC errors, how to read an ADC data sheet, and how to choose the right ADC. Includes the latest information about ADC products and technology.
Fundamentals of Designing with Digital to Analog Converters - BACK BY POPULAR DEMAND: An update to The Fundamentals of the Digital to Analog Converter (DAC) webcast, including basic DAC architectures, understanding DAC errors, how to read a DAC data sheet, how to choose the right DAC. Includes the latest on DAC technology.
Demystifying the JESD204B High-speed Data Converter-to-FPGA interface - This webcast will provide an overview of the JESD204 standard from its original version up to the current "B" revision. In addition, common "high-performance metrics" that are associated with high-speed serial interfaces such as JESD204 will be described. Topics covered in this webcast will also be useful for applications that use similar high-speed serial interfaces.
The Latest on Driving ADCs Differentially: Part 2 - The second of a 2-part series addressing how to select the right differential ADC driver for your design, this webinar takes the basic concepts presented in part 1 and uses them to select the driver and design driving circuits.
The Latest on Driving ADCs Differentially: Part 1 - The first of a 2-part series addressing how to select the right differential ADC driver for your design, this webinar looks at the basics of driving ADCs, including errors in sampled data systems, such as distortion and noise; ENOB; differential signaling definitions and advantages; and ADC driver architectures.
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