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Practical Techniques to Avoid Instability Due to Capacitive LoadingBy Soufiane Bendaoud
(soufiane.bendaoud@analog.com)
As will be seen, the op amp is most prone to instability when it is configured as a unity-gain follower, either because (a) there is no attenuation in the loop, or (b) large common-mode swings, though not substantially affecting accuracy of the signal gain, can modulate the loop gain into unstable regions. The ability of an op amp to drive capacitive loads is affected by several factors: - the amplifier’s internal architecture (for example, output impedance, gain and phase margin, internal compensation circuitry)
- the nature of the load impedance
- attenuation and phase shift of the feedback circuit, including the effects of output loads, input impedances, and stray capacitances.
Among the parameters cited above, the amplifier output impedance, represented by the output resistance, R = 0 will drive any capacitive load without phase degradation._{O}To avoid sacrificing performance with light loads, most amplifiers are not heavily compensated internally for substantial capacitive loads, so external compensation techniques must be used to optimize those applications in which a large capacitive load at the output of the op amp must be handled. Typical applications include sample-and-hold amplifiers, peak detectors, and driving unterminated coaxial cables. Capacitive loading, as shown in Figures 1 and 2, affects the R. The loaded gain can be expressed as follows:_{O}and The –20 dB/decade slope and 90° lag contributed by the pole, added to the –20 dB slope and 90° contributed by the amplifier (plus any other existing lags), results in an increase in the rate of closure (ROC) to a value of at least 40 dB per decade, which, in turn, causes instability. This note discusses typical questions about the effects of capacitive loads on the performance of some amplifier circuits, and suggests techniques to solve the instability problems they raise.
Figure 3 shows a commonly used compensation technique, often dubbed C; and a small capacitor, _{L}C, inserted in the feedback loop, provides a high frequency bypass around _{f}C._{L}To better understand this technique, consider the redrawn feedback portion of the circuit shown in Figure 4. VB is connected to the amplifier’s minus input.
Think of the capacitors, _{ } and C, as open circuits at dc, and shorts at high frequencies. With this in mind, and referring to the circuit in Figure 4, let’s apply this principle to one capacitor at a time._{L}
C_{f }shorted, R<<_{x } R_{f }, and R<<_{o } R, the pole and zero are functions of _{in}C, _{L}R, and _{o}R._{x}
Thus, and
C open, the pole and zero are a function of _{L}C._{f}
Thus, By equating the pole in Case 1 to the zero in Case 2, and the pole in Case 2 to the zero in Case 1, we derive the following two equations: The formula for A_{cl}_{ }(amplifier closed-loop gain, 1+R). By experimenting, it was found that the 1/_{f}/R_{in}A term needed to be included in the formula for _{cl}C. For the above circuit, these two equations alone will allow compensation for any op amp with any applied capacitive load._{f}Although this method helps prevents oscillation when heavy capacitive loads are used, it reduces the closed-loop circuit bandwidth drastically. The bandwidth is no longer determined by the op amp, but rather by the external components, C , producing a closed-loop bandwidth of: _{f}f_{–3 dB} = 1/(2πC)._{f}R_{f}A good, practical example of this compensation technique can be seen with the
AD8510, an amplifier that can safely drive up to 200 pF while still preserving a 45° phase margin at unity-gain crossover. With the AD8510 in the circuit of Figure 3, configured for a gain of 10, with a 1-nF load capacitance at the output and a typical output impedance of 15 ohms, the values of C, computed using the above formulas, are 2 ohms and 2 pF. The square wave responses of Figures 6 and 7 show the fast response with uncompensated ringing, and the slower, but monotonic corrected response._{f}
In Figure 7, note that, because R should always be kept suitably small to avoid excessive output swing reduction and slew-rate degradation._{x}
Here a resistor, R
The output signal will be attenuated by the ratio of the series resistance to the total resistance. This will require a wider amplifier output swing to attain full-scale load voltage. Nonlinear or variable loads will affect the shape and amplitude of the output signal.
Depending on the capacitive load, application engineers usually adopt empirical methods to determine the correct values for C. The principle here is to resistively load down the output of the amplifier for frequencies in the vicinity at which peaking occurs—thus snubbing down the amplifier’s gain, then use series capacitance to decrease the loading at lower frequencies. So, the procedure is to: check the amplifier’s frequency response to determine the peaking frequency; then, experimentally apply values of resistive loading (_{s}R) to reduce peaking to a satisfactory value; then, compute the value of _{s}C for a break frequency at about 1/3 the peak frequency. Thus, _{s}C = 3/(2π_{s}f), where _{p}R_{s}f is the frequency at which peaking occurs._{p}These values can also be determined by trial and error while looking at the transient response (with capacitive loading) on an oscilloscope. The ideal values for C will yield minimum overshoot and undershoot. Figure 12 shows the output response of the
AD8698 with a 68-nF load in response to a 400-mV signal at its positive input. The overshoot here is less than 25% without any external compensation. A simple snubber network reduces the overshoot to less than 10%, as seen in Figure 13. In this case, _{s}R and _{s}C are 30 ohms and 5 nF, respectively._{s}
Another popular application in which significant capacitance may appear at the inputs of the op amp is in filter design. Some engineers may put a large capacitor across the inputs (often in series with a resistor) to prevent RF noise from propagating through the amplifier—overlooking the fact that this method can lead to severe ringing or even oscillation. To better understand what is going on in a representative case, we analyze the circuit of Figure 14, unfolding the equivalent of its feedback circuit (input, which gives a pole located at
This function indicates that the f is well below the open-loop unity-gain frequency, the system becomes unstable. This corresponds to a rate of closure of about 40 dB/decade. The rate of closure is defined as the magnitude of the difference between slopes of the open-loop gain (dB) plot (–20 dB/decade at most frequencies of interest) and that of 1/β, in the neighborhood of the frequency at which they cross (loop gain = 0 dB)._{p}To cure the instability induced by R_{2}, providing a zero which can be matched with the pole, f, to lower the rate of closure, and thus increase the phase margin. For a phase margin of 90°, pick _{p}C =(_{f}R_{1}/R_{2})C_{1}.Figure 15 shows the frequency response of the AD8605 in the configuration of Figure 14.
You can determine the amount of uncompensated peaking using the following equation: where f is the breakpoint of the 1/β curve, and _{z}C is the total capacitance—internal and external—including any parasitic capacitance._{1}The phase margin (Φ The AD8605 has a total input capacitance of approximately 7 pF. Assuming the parasitic capacitance is about 5 pF, the closed-loop gain will have a severe peaking of 5.5 dB, using the above equation. In the same manner, the phase margin is about 29°, a severe degradation from the op amp’s natural phase response of 64°.
The board layout can be a major source of stray input capacitance. This capacitance occurs at the input traces to the summing junction of the op amp. For example, one square centimeter of a PC board, with a ground plane surrounding it, will produce about 2.8 pF of capacitance (depending on the thickness of the board). To reduce this capacitance: Always keep the input traces as short as possible. Place the feedback resistor and the input source as close as possible to the op amp input. Keep the ground plane away from the op amp, especially the inputs, except where it is needed for the circuit and the noninverting pin is grounded. When ground is really needed, use a wide trace to ensure a low resistance path to ground.
In Figure 18, R provide enough closed-loop gain at high frequencies to stabilize the amplifier, and _{A}C_{1} brings it back to unity at low frequencies and dc. Calculating the values of R and _{B}R is fairly straightforward, based on the amplifier’s minimum stable gain. In the case of the
OP37, the amplifier needs a closed-loop gain of at least 5 to be stable, so _{A}R = 4_{B}R for β = 1/5. For high frequencies, where _{A}C_{1} behaves like a direct connection, the op amp thinks it’s operating at a closed-loop gain of 5, and is therefore stable. At dc and low frequencies, where C_{1} behaves like an open circuit, there is no attenuation of negative feedback, and the circuit behaves like a unity-gain follower.The next step is to calculate the value of capacitance, Figure 19 shows the output of the OP37 in response to a 2-V p-p input step. The values of the compensation components are chosen using the equations above, with
R for minimum stable gain. The capacitance value, _{A}C_{1}, is calculated in the same way as for the noninverting case.
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