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Successive-Approximation ADCs: Ensuring a Valid First Conversion
By Steven Xie
Figure 1. Basic SAR ADC architecture.
After power-up and initialization, a signal on CONVERT starts the conversion cycle. The switch closes, connecting the analog input to the SHA, which acquires the input voltage. When the switch opens, the comparator determines whether the analog input, which is now stored on the hold capacitor, is greater than or less than the DAC voltage. To start, the most significant bit (MSB) is on, setting the DAC output voltage to midscale. After the comparator output has settled, the successive-approximation register turns off the MSB if the DAC output was larger than the analog input, or keeps it on if the output was smaller. The process repeats with the next most significant bit, turning it off if the comparator determines that the DAC output is larger than the analog input, or keeping it on if the output was smaller. This binary search continues until every bit in the register is tested. The resulting DAC input is a digital approximation of the sampled input voltage, and is output by the ADC at the end of the conversion.
Factors Related To SAR Conversion Code
Power Supply Sequencing
Data Access During Power Supply Ramp
Figure 2. Reading data during DVCC ramp-up.
SAR ADC Initialization with Reset
Establishing the Reference Voltage
Figure 3. AD765x-1 reference circuit.
Make sure that the voltage on REF or REFCAP has settled before the first conversion. The slew rate and settling time varies for different reservoir capacitors, as shown in Figure 4.
Figure 4. Voltage ramp on AD7656-1 REFCAPA/B/C pins with different capacitors.
In addition, a poorly designed reference circuit can cause serious conversion errors. The most common manifestation of a reference problem is “stuck” codes, which may be caused by the size and placement of the reservoir capacitor, insufficient drive strength, or a large amount of noise on the input. Voltage Reference Design for Precision Successive-Approximation ADCs by Alan Walsh (Analog Dialogue Volume 47, Number 2, 2013) provides details regarding reference design for SAR ADCs.
Analog Input Settling Time
Pay special attention to settling time in multiplexed applications. After the multiplexer switches, make sure to allow enough time for the analog input to settle to the specified accuracy before the conversion starts. When using the AD7606 with a multiplexer, allow at least 80 µs for the ±10-V input range and 88 µs for the ±5-V range to give the selected channel enough time to settle to 16-bit resolution. Front-End Amplifier and RC Filter Design for a Precision SAR Analog-to-Digital Converter by Alan Walsh (Analog Dialogue Volume 46, Number 4, 2012) provides additional details regarding amplifier selection.
Analog Input Range
Figure 5. Fully differential input with common-mode voltage.
For example, the AD7960 18-bit, 5-MSPS SAR ADC’s differential input range is –VREF to +VREF, but both VIN+ and VIN− referred to ground should be in the –0.1 V to VREF + 0.1 V range, and the common-mode voltage should be around VREF/2, as shown in Table 1.
Table 1. Analog Input Specifications for the AD7960
Bringing the SAR ADC Out of Power-Down or Standby Mode
Figure 6 shows that when STBY and RANGE return high, the AD7606 goes from full shutdown mode into normal mode and is configured for the ±10-V range. At this point, the REGCAPA, REGCAPB, and REGCAP pins power up to the correct voltages as outlined in the data sheet. When placed in standby mode, the power-up time is approximately 100 μs, but it takes approximately 13 ms in external reference mode. When powered up from shutdown mode, a RESET signal must be applied after the required power-up time has elapsed. The data sheet specifies the time required between power-up and a rising edge on RESET as tWAKE-UP SHUTDOWN.
Figure 6. AD7606 initialization timing.
SAR ADCs with Latency Delay
For example, the AD7985 features two conversion modes of operation: turbo and normal. Turbo mode, which allows the fastest conversion rate of up to 2.5 MSPS, does not power down between conversions. The first conversion in turbo mode contains meaningless data, and should be ignored. In normal mode, on the other hand, the first conversion is meaningful.
For the AD7682/AD7689, the first three conversion results after power-up are undefined, as a valid configuration does not take place until after the second EOC. Therefore, two dummy conversions are required, as shown in Figure 7.
Figure 7. General timing for AD7682/AD7689.
When using the AD765x-1 in hardware mode, the logic state of the RANGE pin is sampled on the falling edge of the BUSY signal to determine the range for the next simultaneous conversion. After a valid RESET pulse, the AD765x-1 defaults to operating in the ±4 × VREF range, with no latency problem. If, however, the AD765x-1 operates in ±2 × VREF range, one dummy conversion cycle must be used to select the range at the first falling edge of BUSY.
In addition, some SAR ADCs, such as the AD7766/AD7767 oversampled SAR ADC, have postdigital filters that cause additional latency delay. When multiplexing analog inputs to this type of ADC, the host must wait the full digital filter settling time before a valid conversion result can be achieved; the channel can be switched after this settling time.
As shown in Table 2, the latency of the AD7766/AD7767 is 74 divided by the output data rate (74/ODR). When running at the maximum output data rate of 128 kHz, the AD7766/AD7767 allows a 1.729-kHz multiplexer switching rate.
Table 2. Digital Filter Latency of AD7766/AD7767
Digital Interfacing Timing
Kester, Walt. “Which ADC Architecture Is Right for Your Application?” Analog Dialogue, Volume 39, Number 2, 2005.
Walsh, Alan. “Front-End Amplifier and RC Filter Design for a Precision SAR Analog-to-Digital Converter.” Analog Dialogue, Volume 46, Number 4, 2012.
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