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Download this article in PDF format. (817KB) Synchronous Inverse SEPIC Topology Provides High Efficiency Buck/Boost Voltage Converters In many markets,
demand is increasing for efficient noninverting dc-to-dc converters that
can operate in either buck or boost mode, decreasing or increasing the
input voltage to a desired regulated voltage—with minimal cost and
component count. The inverse SEPIC (
Primary switch QH1
and secondary switch QL1 operate in opposite phase from one another. During
the
During the
Applying the principles
of
This suggests that
if the duty cycle is greater than 0.5, a higher voltage will be regulated
at the output ( V
in a lossless system; the dc value of the current through the output inductor
(L1B) is equal to _{OUT}I; and the dc value of the current
through the ground-reference inductor (L1A) is _{OUT}I
× _{OUT}V/_{OUT}V. The energy-transfer
capacitor also provides dc blocking from _{IN}V to _{IN}V.
This property can be attractive when there is a risk of a shorted output._{OUT}The analysis also shows that the output current in the inverse SEPIC is continuous, yielding a lower peak-to-peak output voltage ripple for a given output capacitor impedance. This allows the use of smaller, less costly output capacitors as compared to the capacitors needed to meet the same ripple requirement with discontinuous output current topologies. Typically
the secondary switch (QL1) is a unidirectional power diode, which limits
the peak efficiency of this topology. However, with a single channel of
the Analog Devices ADP1877 dual-channel synchronous switching controller
(see Appendix),
an inverse SEPIC can be designed in a Figure 4 shows the
power stage of the fully synchronous inverse SEPIC configuration, as implemented
with the ADP1877 and requiring only three small, inexpensive additional
components (C
The ideal steady-state
waveforms of the inverse SEPIC are shown in Figure 5. The Channel-1 switch
node, SW1, (see Figure A in the Appendix) is toggled between V during the _{OUT}on time and 0 V during the
off time. Connecting charge-pump capacitor, C_{BST}, to
SW1 imposes a voltage approximately equal to V + _{IN}V
+ 5 V on the bootstrapped upper rail of the high-side internal driver
(BST1 pin) and the output of the high-side driver (DH1 pin) during the
on time, thus enhancing the primary floating _{OUT}D, ensures that C_{DRV}_{BLK1}
has approximately V+ _{OUT }V(_{FWD}D)
across it during steady-state output, as referenced from the DH1 pin of
the ADP1877 to the gate of QH1. The voltage across C_{DRV}_{BLK1} keeps
the primary switch from developing a gate-to-source voltage that is higher
than its threshold during the off time when the V._{OUT}
The ADP1877 has
a
Even though the
inductors are coupled, it is undesirable for the coupling to be tight
enough to transfer significant energy from one winding to the other through
the core. This can be avoided by finding the leakage inductance ( C)
such that the magnitude of its complex impedance is one tenth of the complex
series impedance of the leakage inductance and the resistance (DCR) of
a single winding, as designated in Equations 2, 3, and 4. Designing the
circuit to conform to this relationship minimizes the energy transfer
through the coupled core. The leakage inductance can be calculated from
the coupling coefficient, commonly found on coupled-inductor data sheets._{BLK2}
A 1:1 turns ratio
is desirable because it requires half the inductance for each winding
that discrete inductors would need for a given level of output voltage
ripple.
First, many complex
impedance interactions at the resonant frequency (
At this frequency
there can be 300° or more of "high- f. Damping this resonance is largely dependent on
the output loading resistance and the coupled inductor's dc resistance.
To a lesser extent, damping is dependent on the _{RES}equivalent series resistance
(ESR) of the energy-transfer capacitor, and the on resistance
of the power MOSFETs (QHl and QL1). Therefore, as the output load resistance
varies, one should not be surprised to see the signature of the closed-loop
transfer function change dramatically at this frequency.The coupling coefficient
is often not a well controlled parameter, so the target crossover frequency,
f,
assuming _{RES}f is less than the switching frequency,
_{RES}f. Standard "Type II" compensation—with
two poles and a zero—can be used when _{SW}f is
set appropriately._{UNITY}
Figure 6 shows the equivalent circuit of the ADP1877's feedback loop when employed in a synchronous inverse SEPIC buck/boost topology. The upper box contains the power stage and current loop; the lower box contains the voltage feedback loop and compensation circuitry.
The compensation-component values in the lower box can be calculated as follows:
R is the minimum
output load resistance. _{LOAD}A is the current sense gain,
which, with the ADP1877, is selectable in discrete steps from 3 V/V to
24 V/V. _{CS}G is the transconductance of the error amplifier,
550 μs
for the ADP1877. _{m}V is the reference voltage that
is tied to the positive input of the error amplifier, 0.6 V for the ADP1877._{REF}
R,
the resistance of the secondary switch when enhanced. It is expected that
the highest crossover frequency occurs when this resistance and the duty
cycle, _{DS(ON)}D, are at their lowest.To ensure that the
compensation clamp voltage is not reached at maximum output current, the
highest value of current-sense gain (
where ∆
If excessive slope compensation is added, the equations in this section will be less accurate: the dc gain will decrease and the dominant pole location—due to the output filter—will increase in frequency.
^{2} must be taken into
account.By setting ^{3}
assuming f was set appropriately._{UNITY}
It is noteworthy
that as Q of the sampling poles
also decreases. If this, in conjunction with other related tolerances,
results in a Q of less than 0.25, one should perform a simulation
to ensure the converter does not have excessive slope compensation and
is not "too voltage mode" with tolerance considered. The value
of R_{RAMP} must result in a current between 6 μA
and 200 μA
into the ADP1877's RAMP pin, as calculated with Equation 14.
The ac component of the current through both switches is
With these values
known, one can quickly calculate the rms values of the current through
each switch. In conjunction with the
Calculating switching
loss in the primary switch accurately is beyond the scope of this paper,
but it should be noted that, in transitioning from high-resistance- to
low-resistance states, the voltage across the MOSFET will swing from ~ V to ~0 V, and the current through the device will
swing from 0 A to _{OUT}I[1/(1 – D)]. Switching loss
can be the predominant loss with swings of these magnitudes, a factor
one should be aware of when picking a MOSFET for which the reverse transfer
capacitance (_{OUT}C) and _{RSS}R are
inversely proportional._{DS(ON)}The The peak-to-peak
output-voltage ripple (∆
The rms value of
the current through the output capacitor (
The peak-to-peak
inductor current (∆ For synchronous
inverse SEPICs implemented with the ADP1877, the input voltage plus the
output voltage must not exceed 14.5 V because the charge-pump capacitor
is connected to the switch node, which reaches V when the primary switch is conducting._{OUT}
The bill of materials for the relevant power components associated with Figure 8 is seen in Table 1; it includes only common off-the-shelf components. A comparable asynchronous design using an industry-leading Schottky diode with a low forward-voltage drop in place of QL1 is almost 10% less efficient at full load at both input voltages. The asynchronous design would also be larger and more expensive and would be likely to require a costly heat sink.
Analog Dialogue. 41-2,
^{TM}
(proprietary architecture of Analog Devices, Inc.) dual-channel, switching
controller with integrated drivers that drive N-channel synchronous power
MOSFETs. The two PWM outputs are phase-shifted by 180°, which reduces
the input rms current, thus minimizing required input capacitance.
The boost diodes are built into the ADP1877, thus lowering the overall component count and system cost. The ADP1877 can be set to operate in pulse-skip high-efficiency mode under light load, or in PWM continuous conduction mode. The ADP1877
includes externally adjustable soft start, output overvoltage protection,
externally adjustable current limit, power good, and a programmable oscillator
frequency that ranges from 200 kHz to 1.5 MHz. The ADP1877 provides an
output voltage accuracy of ±0.85% from –40°C
to +85°C and ±1.5% from –40°C
to +125°C junction temperature. Powered by a 2.75-V to 14.5-V supply,
it is available in a 32-lead, 5 mm ×
5 mm LFCSP package.
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