Volume 36, Number 6, November-December, 2002
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Bus switchesoften called digital switchesare products designed for connecting to high speed digital buses. Characterized by sub-nanosecond propagation delay and fast switchingand introducing no additional noise or dc power dissipationthey are ideally suited for voltage translation, hot swapping, hot plug, bus or capacitance isolation, and many other applications. In addition, their design makes them useful in many analog applications. The key features that make them suitable for so many different applications include low on-resistance, low capacitance, and low propagation delay. This discussion will consider the architecture and characteristics of bus switchesand explain many of their uses.
What is a bus switch?
Figure 1. Bus switch channel.
When the switch is enabled (BE at 0), its gate is driven to VCC. If VGS (or VGD)i.e., VCC VIN, is greater than the transistor threshold voltage (usually about 1 V) the channel will switch to the low-resistance on condition (a few ohms). However, as VGS approaches the threshold voltage, the device approaches its saturation region and becomes highly resistive; Figure 2 shows a typical plot of on-resistance versus input voltage as a function of VCC (ADG3257). When in saturation, the output voltage will be limited to VCC VTH.
Figure 2. On-resistance of ADG3257 bus switch vs. input voltage (VA or VB).
Figure 3 is a plot of output voltage versus input voltage for a typical bus switch with inputs and supply voltages in the 5-V range. When VGS becomes less than about 1 V, the switch channel begins to saturate and the voltage clamps to VCC VTH. So, in this example, for VCC = 5 V, the output follows the input up to about 4 V. Beyond this input voltage, VOUT is held at VCC VTH. This clamping tendency turns out to be a very useful feature of a bus switch; its advantages and use will be discussed in more detail later.
Figure 3. VOUT vs. VIN for the ADG3257 bus switch with VCC in the 5-V range.
Key features affecting applications of bus switch devices are: on-resistance, capacitance associated with the channel, and propagation delay. On-resistance of such devices is usually very lowtypically a few ohms. The capacitance, which needs to be kept as low as possible, is typically less than 10 pF in the on condition. Both capacitance and on-resistance parameters affect the propagation delay through the switch channel.
Practically all of the propagation delay of a bus switch in the on condition, driven by a low impedance voltage source, comes from the RC delay of the RON of the switch and the load capacitancetypically it is in the sub-nanosecond region and is much smaller than the rise/fall times of the driving signals. In a system, propagation delay of the digital switch is determined by the circuit impedance on the driving side of the switch and its interaction with the load on the driven side.
Where would we use a bus switch?
Using a digital bus switch for bus isolation
If a bus switch is placed between each load on the bus and the bus itself, then the load is isolated from the bus when the switch is disabled. Because the bus switch can pass significant amounts of current in either direction when enabled, without adding significant propagation delay for signals that pass through it, it is a viable solution to the bus isolation problem. Figure 4 shows a generalized situation, and Figure 5 shows a specific solution to a memory bank drive problem with a quad 2:1 multiplexer bus switch.
Figure 4. A bus switch can isolate Load B from the rest of the bus.
Figure 5a shows an array of memory banks in which each address and data signal is loaded by the sum of the individual loads. Now, if a bus switch is used (the ADG3257 quad 2:1 multiplexer/demultiplexer in this example) as shown in Figure 5b, then the output load on the memory address and data bits is halved. This isolation can provide a near-doubling of the speed at which the selected bank’s data can flow, because the capacitance loading is halved and the switches introduce negligible propagation delay. Bus noise is also markedly reduced.
Figure 5. Reducing memory bank loading. a) The address and data lines are heavily loaded when all memory banks are permanently connected to the bus. b) When the ADG3257 is used to switch between different memory bank pairs, access time and noise are both reduced.
Figure 6. Using the ADG3257 to switch and level translate between a 3.3-V controller and 5-V data converter.
As discussed above, if the VGS voltage is reduced to less than 1 V, the switch channel begins to saturate and the output voltage clamps to VCC VTH. That is, the output follows the input up to the vicinity of this voltage and, for higher input voltages, VOUT is held at VCC VTH. Figure 7 shows an output-input plot of the same switch as in Figure 3, but focused on VCC in the 3.3-V region. This behavior makes bus switch devices suitable for interfacing applications calling for level translation.
Figure 7. VOUT vs. VIN for the ADG3257 bus switch with VCC in the 3-V range.
In the example of Figure 6, the user may wish to apply a 3.3-V DSP or microcontroller as a control device in an application for which reasonable analog performance requires that the ADC or DAC or other device operate from, say, a 5-V supply. Unless the microcontroller has inputs that can tolerate the 5-V device’s output levels, the circuits will not be able to communicate properly. With the bus switch of Figures 3 and 7 connected between the devices, as a voltage translator, bidirectional communication is possible without risk of damaging the lower-supply device. The combination of the diode, connected in series with the 5-V supply, and the bus switch’s clamp voltage provides a drop fairly close to the required 5-V-to-3.3-V (left to right) without impeding 3.3-V communication (right to left).
Similarly, the device could be used to level-translate between 3.3-V and 2.5-V systems. A LVTTL VOH level for a 2.5-V output is 2 V, while the LVTTL VIH level required by the 2.5-V device is 1.7 V, so a 5-V bus switch operating at a lower supply voltage can easily meet these requirements.
Because a bus switch is a simple FET, the signal path is bidirectional; i.e., the inputs and outputs are interchangeable. However, information cannot always be communicated bidirectionally; it is dependent on supply. Table 1 shows that translations between 5 V↔3.3 V and 3.3 V↔2.5 V may be used to communicate bidirectionally between devices operating from different supplies, but the other two options (2.5 V→1.8 V, 3.3 V→1.8 V) cannot be employed for both directions. For further details, see the ADG3247 data sheet.
Table 1. Bus Switch Devices and Their Level-Translation Capabilities.
1SEL pin tied to logic low. For more information on SEL pin, see ADG3245/6/7 data sheets.
2Requires external diode.
As explained earlier, the threshold voltage, VTH, is approximately 1 V, so with 2.5-V supply, the maximum output of the bus switch will be 1.5 V, which is insufficient to meet the 1.7-V VIH input requirement of a 2.5-V device (Figure 8). Similarly, when translating between 3.3 V and 1.8 V, the maximum output of the bus switch will be 1.5 V, so again the voltage level is not sufficiently high for a 3.3-V device to recognize it as logic high. Therefore, the signal path can be relied on only for unidirectional communication in these cases.
Figure 8. Logic levels compared for different supply voltages.
How many "bits"?
Can a bus switch be used to switch analog signals?
Figure 9. Charge injection for a typical bus switch (ADG3257).
Thus, bus switches need not be confined to bus switching applications or used solely for switching digital signals. They can also find many uses in switching analog signals, within the limitations of
How are bus switches useful in hot swap applications?
Figure 10. Hot swapping with the ADG3246 bus switch.
And how about hot plug?
Figure 11. Using the ADG3247 in a hot-plug application.
The benefits of a flow-through pinout architecture
Figure 12. Flow-through pin arrangement.
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