Quad-SHARC DSP in Ceramic Quad Flatpack
Smaller, Faster, Cheaper AD14060A 480-MFLOPS DSP Powerhouse
AD14060 Quad-SHARC packs 480 MFLOPS into 60% less space.
The AD14060 Quad-SHARC, the first in a family of high-performance DSP multiprocessor modules, combines four ADSP-21060 microcomputers in an architecture and package designed to optimize their performance as a computational team.
It is provided to meet the ever-growing computational needs of complex systems ranging from medical image processing to multi-sensor missile seekers, performing complex tasks without using excessive space. But handling fast clock rates and large numbers of inputs/outputs requires capabilities that stress conventional IC packages and PCB interconnect. The advanced packaging used for the AD14060 provides the necessarily complex chip-to-chip interconnects inside a single package; optimizes performance with embedded ground planes, low inductance leads, and controlled-impedance traces; simplifies back-end assembly and test; reduces board, connector, and enclosure costs; and best of all, enables system-level cost savings.
Leveraging the built-in multiprocessing capabilities of the ADSP-2106x DSP, the Quad-SHARC puts 480 MFLOPS peak processing (320 MFLOPS sustained) into 60% less space than is achievable with conventional packaging. Electrical performance characteristics (e.g., ground bounce) are improved by embedding ground planes and using proprietary package design and assembly processes to minimize lead inductance. Thermal performance is excellent with a qJC of only 0.36°C/W, and designers have the option of cavity-up or cavity-down mounting. Finally, assembly yield is improved by shipping parts with the leadframe intact to ensure that lead coplanarity is undisturbed in shipment/handling; incidentally, the AD14060 design has a wider lead pitch (0.025") than do the discretes.
The general-purpose architecture of the AD14060 offers flexibility to system designers in interfacing the module to external memory (SRAM, EPROM), and peripheral devices such as host processors, standard bus interfaces, custom interfaces, and additional SHARCs. For handling sensor data I/O or for communicating with other clusters of SHARCs, twelve 40-MByte/s I/O ports are available. The table lists some of the AD14060's salient specifications:
|Performance||480 MFLOPS Peak, 320 sustained|
|Internal memory||16 Mbit shared SRAM|
|Addressable off-chip memory||4 gigawords|
|DMA bandwidth||480 MByte/s|
|Parallel external buses||32-bit address, 48-bit data|
|Serial ports||5 (4 independent, 1 common)|
|Link ports||Twelve 40 Mbyte/s|
|Package (hermetic)||308-lead ceramic quad flatpack|
|Body size||2.05" (52 mm)|
|Lead pitch||0.025" (0.635 mm)|
|Temperature range options||-40 to +100°C, -55 to +125°C|
|Supply voltage options||3.3 V, 5 V|
|Price (1000s)||from $1984|
Application Benefits: For applications such as image processing, radar surveillance, industrial instrumentation, cellular base stations, or missile seekers, maximum processing power in minimum size is often a critical requirement. Many such systems are based on standard board form factors such as the VME bus. A system with multiple, or even hundreds, of DSPs typically requires multiple boards and chassis, calling for box-to-box interfaces and cabling, which adds expense, complication, and degraded performance. Designers can reduce these concerns by including more DSPs (with optimized physical and electrical mounting) per board, and where possible containing the system in a single box. With a single backplane bus-and cabling eliminated-the system cost, performance, and time-to-market are greatly improved.
Performance improvements can also be seen at the board level. For example, high-speed digital systems can suffer from ground bounce problems due to large numbers of signals switching simultaneously and momentarily shifting the ground reference level between the chip and the board. The MCM has reduced ground bounce concerns by embedding ground planes in the multi-layer package and providing very low-inductance paths from the silicon. The internal multi-DSP interconnections have also been routed with controlled length and separation, and the use of controlled impedance interconnect. With this piece of the design already optimized, the designer is free to tackle the many other system issues.
Another common system design need (often experienced in military designs) is to retrofit existing designs with improved processors. Processor improvements are driven by increased requirements in sensor interfaces, more complex algorithms, and additional features. In the case of a missile interceptor, it was once sufficient to get close enough to an incoming target to hopefully destroy it by exploding nearby; nowadays, direct hit is the goal. Another example is replacing single sensors (IR, radar, visible, etc.) by multiple sensors for all-weather, all-threat capability. In most cases, the existing missile bodies must be upgraded with new electronics; perhaps 10-100 times the processing power has to go onto the same-size circuit board (such as a 100-mm diameter circle). Modules like the AD14060 can help to meet the increased performance-density issues that these applications face.
For evaluation and hardware/software development, Bittware Research Systems produces a Blacktip-MCM board. It is an ISA card with one AD14060, plus memory and I/O expansion options, and supported by standard SHARC DSP development tools.
The AD14060 was designed by Glenn Romano and Roy Buck at our Greensboro, NC facility.
33 N. Main St., Concord, NH 03301, (603) 226-6667, www.bittware.com