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Ask The Applications Engineer -3
by James Bryant
A. An excellent solution to this common problem is to ship the signal as frequency using a voltage-to-frequency converter (VFC), a circuit whose output is a frequency proportional to its input. It is relatively easy to send a frequency signal over a long transmission path without interference via optical isolators, optical fibre links, twisted-pair or co-axial lines, or radio links.
If the data must be digital, the receiver will consist of a frequency counter, easily implemented in a single-chip microcomputer. Frequency is reconverted to analog voltage by a frequency-to-voltage converter (FVC)-generally a VFC configured to perform its inverse function, often using a phase-locked loop.
Q. How does a VFC work?
A. There are two common types: multivibrator-(AD537) and charge-balance (AD650) VFCs.*
In the multivibrator type, the input voltage is converted to a current which charges and discharges a capacitor. The switching thresholds are set by a stable reference, and the output, which has unity mark-space ratio, is a frequency proportional to the input.
The charge-balance VFC uses an integrator, a comparator and a precision charge source. The input is applied to the integrator, which charges. When the integrator output reaches the comparator threshold, the charge source is triggered and a fixed charge is removed from the integrator. The rate at which charge is removed must balance the rate at which it is being supplied, so the frequency at which the charge source is triggered will be proportional to the input to the integrator.
Q. What are the advantages and disadvantages of the two types?
A. The multivibrator is simple and cheap, demands little power, and has unity mark-space (M-S) output-very convenient with some transmission media. But it is less accurate than the charge-balance type and cannot integrate negative input transients.
The charge-balance type is more accurate, and negative input transients are integrated to contribute to the output. It has more-demanding supply requirements and a lower input impedance, and its output is a pulse train, not a unity M-S square wave.
Q. What are the important types of error in a VFC?
A. The same three as in most precision circuitry: offset errors, gain errors and linearity errors-and their variation with temperature. As with most precision circuitry, offset and gain can be trimmed by the user, but linearity cannot. However, the linearity of VFCs is normally very good (if the capacitors are properly chosen-see below).
Q. How do you trim gain and offset in a VFC?
A. The procedure suggested by theory is to trim offset first at zero frequency and then gain at full scale (FS). But this can give rise to problems in recognizing zero frequency, which is the state when the VFC is just not oscillating. It is therefore better to trim offset with a small input (say 0-1% FS) and adjust for a nominal frequency, then trim gain at FS, and then repeat the procedure once or twice.
For example, suppose a VFC is being used with FS of 100 kHz at 10-volt input. Ideally, 10 V should give 100-kHz output and 10-mV input should give 100 Hz. Offset is, therefore, trimmed for 100 Hz with 10 mV applied; gain is then trimmed to give 100 kHz at 10 V. But gain error affects the 10-mV offset trim slightly, so the procedure may have to be repeated to reduce the residual error.
If a VFC is used with software calibration a deliberate offset is often introduced so that the VFC has a definite frequency for zero input voltage. The microcomputer measures the VFC outputs at 0 V and FS inputs and computes the offset and scale factor. It may also be necessary to reduce the gain so that the VFC cannot try to exceed its maximum rated frequency.
Q. What circuit precautions are necessary when using a VFC?
A. Apart from the usual precautions necessary with any precision analog circuitry (grounding, decoupling, current routing, isolation of noise, etc., a subject for a book, not a paragraph) the main precautions necessary when using a VFC are the choice of capacitor and separation of the input and output.
The critical capacitors in a precision VFC (the multivibrators timing capacitor, and the monostable timing capacitor in a charge-balance type) must be stable with temperature variation. Furthermore, if they suffer from dielectric absorption, the VFC will be nonlinear and may have poor settling time.
If a capacitor is charged, discharged and then open-circuited it may recover some charge. This effect, known as dielectric absorption (DA), can reduce the precision of VFCs or sample-hold amplifiers using such capacitors. VFCs and SHAs should therefore use Teflon or polypropylene, or zero- temperature-coefficient (NPO, COG) ceramic capacitors with low DA.
Coupling between output and input of a VFC can also affect its linearity. To prevent problems, decoupling practices and the usual layout precautions should be observed. This is critically important with opto couplers, which require high current drive (10-30 mA).
Q. How do you make a frequency-to-voltage converter?
A. There are two popular methods: the input frequency triggers the monostable of a charge-balance VFC that has a resistor in parallel with its integration capacitor; or the input frequency can be applied to the phase/frequency comparator of a phase-locked loop (PLL), which uses a VFC (of either type) as its oscillator. The basic principle of the first type is illustrated below.
For each cycle of the input frequency, a charge, Q, is delivered to the leaky integrator formed by R and C. At equilibrium, an equal charge must leak away during each period, T (= 1/f), of the input, at an average rate, I = V/R. Thus, V = Q·f·R.
Though the mean voltage is independent of C, the output ripple is inversely dependent on C. The peak-to-peak ripple voltage, V, is given by the equation, V=Q/C. This indicates that ripple is independent of frequency (assuming that the charge, Q, is delivered in a short time relative to the period of the input). The settling time of this type of FVC is determined by the exponential time constant, RC, from which the time to settle within a particular error band may be calculated.
From these equations, we see that the characteristics of this type of FVC are interdependent, and it is not possible to optimize ripple and settling time separately. To do this we must use a PLL.
The phase-locked-loop FVC illustrated differs from any other PLL in only one respect: the voltage-controlled oscillator of the normal PLL, which must be monotonic but not necessarily linear, has been replaced by a VFC with a linear control law. In the servo system, negative feedback keeps the VFCs output frequency equal to the input frequency. The output voltage, the VFCs input, is accurately proportional to the input frequency.
Designing PLL systems is beyond the scope of this discussion,1 but if a 4000-series CMOS PLL, the 4046, is used just as a phase detector (its VCOs transfer characteristic is not sufficiently linear), we can build the FVC shown here, with an AD654 VFC.
Q. What is a synchronous VFC?
A. A charge-balance VFC with improved linearity and stability, where the monostable is replaced by a bistable, driven by an external clock. The fixed time during which the precision current discharges the integrator is one clock period of the external clock.
A further advantage of the SVFC is that the discharge does not start when the integrator passes the comparator threshold (at a non-critical rate), but on the next clock cycle. The SVFC output is synchronous with a clock, so it is easier to interface with counters, µPs, etc.; it is especially useful in multichannel systems: it eliminates problems of interference from multiple asynchronous frequency sources.
There are two disadvantages. Since the output pulses are synchronized to a clock they are not equally spaced but have substantial jitter. This need not affect the user of a SVFC for a/d conversion, but it does prevent its use as a precision oscillator. Also, capacitive coupling of the clock into the comparator causes injection-lock effects when the SVFC is at 2/3 or 1/2 FS, causing a small (4-6 bit at 18-bit resolution at 1-MHz clock) dead zone in its response. Poor layout or device design can worsen this effect.
Despite these difficulties the improvement in performance produced by the abolition of the timing monostable makes the SVFC ideal for the majority of high-resolution VFC applications.
Q. Can you have a synchronized FVC?
A. Yes, and with very good performance; it is best done with an FVC- connected SVFC and a clock that is common to both ends of the transmission path. If the input signal to a synchronized FVC is not phase related to the clock, severe timing problems can arise, which can only be solved by the use of additional logic (two D flip-flops) to establish the correct phase relationship.1See Gardner, F. M, Phase-lock Techniques, 2nd ed., New York: Wiley,
1979, for more detail; also Analog Devices Analog-Digital Conversion Handbook. *Data sheets are available for any of the Analog Devices products mentioned here.
An Application Note: Operation and Applications of the AD654 V-to-F Converter, is also available without charge.