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クロック＆データ再生
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AN-851: A WiMax Double Downconversion IF Sampling Receiver Design
(pdf, 262 kB)
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AN-757: Acquisition Times of the ADN2812
(pdf, 78 kB)
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AN-746: Supporting FDDI with the ADN2812
(pdf, 76 kB)
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AN-657: ADN2812 Evaluation Board
(pdf, 690 kB)
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AN-636: ADN2819 Evaluation Board
(pdf, 317 kB)
This application note describes the use of the ADN2819 evaluation board. The ADN2819 is a multirate clock recovery, data-retiming device based on a multiloop PLL architecture. The ADN2819 can recover clock and data at
SONET OC-3,OC-12,OC-48,and Gigabit Ethernet data rates as well as 15/14 Forward Error Correction (FEC)for
these rates by using a single reference clock or external crystal oscillator.
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AN-632: Provisionary Data Rates Using the AD9951 DDS as an Agile Reference Clock for the ADN2812 Continuous-Rate CDR
(pdf, 138 kB)
