アプリケーション・ノート (36)
-
AN-1217: Clock Distribution Circuit with Pin-Programmable Output Frequency, Output Logic Levels, and Fanout
(pdf, 203 kB)
- AN-1177: LVDS and M-LVDS Circuit Implementation Guide (pdf, 586 kB)
- AN-1066: Power Supply Considerations for AD9523, AD9524, and AD9523-1 Low Noise Clocks (pdf, 330 kB)
- AN-939: 高い周波数のRF出力信号が得られるAD9912のスーパーナイキスト動作 (Rev. 0, 10/2007) (pdf, 351 kB)
- AN-1079: Determining the Maximum Tolerable Frequency Drift Rate of the AD9548 System Clock in Low Loop Bandwidth Applications (pdf, 210 kB)
- AN-0988: The AD9552: A Programmable Crystal Oscillator for Network Clocking Applications (pdf, 382 kB)
- AN-1061: Behavior of the AD9548 Phase and Frequency Lock Detectors in the Presence of Random Jitter (pdf, 470 kB)
- AN-1064: Understanding the Input Reference Monitors of the AD9548 (pdf, 155 kB)
- AN-0974: Multicarrier TD-SCMA Feasibility (pdf, 634 kB)
- AN-1051: AD9552発振器、周波数アップコンバータのリファレンス・デザイン (pdf, 291 kB)
- AN-1002: The AD9548 as a GPS Disciplined Stratum 2 Clock (pdf, 157 kB)
- AN-0982: The Residual Phase Noise Measurement (pdf, 710 kB)
- AN-0983: Introduction to Zero-Delay Clock Timing Techniques (pdf, 162 kB)
- AN-756: サンプル化システムに及ぼすクロック位相ノイズとジッタの影響 (pdf, 359 kB)
- AN-953: プログラマブルなモジュラスを採用したダイレクト・デジタル・シンセシス（DDS） (Rev. 0, 01/2008) (pdf, 261 kB)
- AN-927: スプリアスとDDS / DACやその他の発生源（スイッチング電源など）との関係の判定 (pdf, 327 kB)
- AN-837: DAC再生フィルタ性能とDDS採用時のクロック・ジッタ性能の関係 (pdf, 528 kB)
- AN-772: リード・フレーム・チップ・スケール・パッケージ（LFCSP）の設計および製造ガイド (pdf, 806 kB)
- AN-769: Generating Multiple Clock Outputs from the AD9540 (pdf, 0)
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AN-823: Direct Digital Synthesizers in Clocking Applications Time
(pdf, 115 kB)
Jitter in Direct Digital Synthesizer-Based Clocking Systems - AN-851: A WiMax Double Downconversion IF Sampling Receiver Design (pdf, 262 kB)
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AN-345: 低周波回路と高周波回路のグラウンド設計
(pdf, 491 kB)
効果的な設計のためにグラウンド経路と信号経路を理解すること。電流は、抵抗ではなくインピーダンスが最小の経路に流れる・・・ - AN-501: アパーチャ不確定性とADCシステム性能 (pdf, 212 kB)
- AN-741: 位相ノイズの知られざる特性 (Rev. 0, 08/2004) (pdf, 1076 kB)
- AN-605: Synchronizing Multiple AD9852 DDS-Based Synthesizers (pdf, 527 kB)
- AN-632: Provisionary Data Rates Using the AD9951 DDS as an Agile Reference Clock for the ADN2812 Continuous-Rate CDR (pdf, 138 kB)
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AN-621: Programming the AD9832/AD9835
(pdf, 202 kB)
This application note details how to program 5 MHz on the output of the AD9832/AD9835 parts. The frequency register,defer register,and command sequence are explained in detail. - AN-342: 高速性と高精度を同時に実現するアナログ信号処理 (pdf, 829 kB)
- AN-280: ミックスド・シグナル（デジタル・アナログ混在）回路の技術 (pdf, 1218 kB)
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AN-557: An Experimenter's Project:
(pdf, 368 kB)
Incorporating the AD9850 Complete DDS Device as a Digital LO Function in an Amateur Radio Transceiver - AN-419: 全機能内蔵ダイレクト・デジタル・シンセサイザAD9850のためのデスクリート、低位相ノイズ、125MHzクリスタル発振器 (pdf, 452 kB)
- AN-237: Choosing DACs for Direct Digital Synthesis (pdf, 1156 kB)
- AN-423: Amplitude Modulation of the AD9850 Direct Digital Synthesizer (pdf, 37 kB)
- AN-587: 複数のAD9850 / AD9851 DDSベースのシンセサイザを同期させる (pdf, 242 kB)
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AN-543: High Quality, All-Digital RF Frequency Modulation Generation with the ADSP-2181 and the AD9850 DDS
(pdf, 49 kB)
- AN-543 - Monaural FM Transmitter (dsp, 20 kB)
- AN-543 - Stereo FM Transmitter (dsp, 25 kB)
- AN-835: 高速A/Dコンバータ（ADC）のテストと評価について (pdf)
実用回路 (6)
- CN0294: Increasing the Number of Outputs from a Clock Source Using Low Jitter LVPECL Fanout Buffers (pdf, 420 kB)
- CN-0243: High Dynamic Range RF Transmitter Signal Chain Using Single External Frequency Reference for DAC Sample Clock and IQ Modulator LO Generation (pdf, 700 kB)
- CN-0186: Phase Coherent FSK Modulator (pdf, 239 kB)
- CN-0140: High Performance, Dual Channel IF Sampling Receiver (pdf, 191 kB)
- CN-0121: Synchronizing Multiple AD9910 1 GSPS Direct Digital Synthesizers (pdf, 384 kB)
- CN-0109: Low Jitter Sampling Clock Generator for High Performance ADCs Using the AD9958/AD9858 500 MSPS/1GSPS DDS and AD9515 Clock Distribution IC (pdf, 114 kB)
技術関連記事 (32)
-
Synchronizing NxN MIMO Basestations to an External Timing Reference
Understand how a high-performance clock generator, in conjunction with one or more integrated transceivers, simplifies overall design and reduces complexity and cost, while resulting in excellent system receive/transmit performance.
(RF DesignLine, 5/10/2010) -
Speedy A/Ds Demand Stable Clocks
by Jeff Keip, Analog Devices, Inc. (EE Times, 3/18/04) -
Design A Clock-Distribution Strategy With Confidence
by Demetrios Efstathiou (Electronic Design, April 27, 2006) -
Understand the Effects of Clock Jitter and Phase Noise on Sampled Systems
... Much of your system's performance depends on jitter specifications, so careful assessment is critical.
by Brad Brannon, Analog Devices (EDN, 12/7/2004) - Low-power direct digital synthesizer cores enable high level of integration
-
Improved DDS Devices Enable Advanced Comm Systems
by Valoree Young, Analog Devices
(Electronic Products, September 2006) -
ADI Buys Korean Mobile TV Chip Maker
(EE Times, 6/7/2006) -
Clocking Requirements for High Speed Data Converters
Wireless infrastructure, broadband and instrumentation applications generally require very high performance clocking circuits. This article will discuss the clocking technologies required.
(Part 1 of 4)
(EE Times Europe, 8/18/09) -
Healthcare at Home (Part II)
A major trend in medicine is to move treatments and monitoring out of the hospital or even the doctor's office and either attach them to the patient or enable it to be done in the home. What can device designers do to aid this effort and what technologies would help to enable it.
(EDN, February 25, 2008) -
DDS Device Provides Amplitude Modulation
by Mary McCarthy, Analog Devices, Inc.
(EDN, September 2, 1999) -
Introducing Digital Up/Down Converters: VersaCOMM™ Reconfigurable Digital Converters
(pdf, 63 kB)
Revolutionize your radio architectures - Digital Up/Down Converters: VersaCOMM™ White Paper (pdf, 97 kB)
- Basics of Designing a Digital Radio Receiver (Radio 101) (pdf, 77 kB)
-
Synchronized Synthesizers Aid Multichannel Systems
by David Brandon and John Kornblum, Analog Devices, Inc. (Microwaves & RF, 9/2005) -
The Year of the Waveform Generator
(Test & Measurement World, 12/1/2005) -
DDS Applications
by Eva Murphy and Colm Slattery, Analog Devices, Inc. (EETimes, 9/26/2005) -
DDS IC Initiates Synchronized Signals
(Microwaves & RF Cover Story, July 2005) -
Digital Waveform Generator Provides Flexible Frequency Tuning for Sensor Measurement
by Colm Slattery, Analog Devices (EDN, 12/17/2004) -
DDS Simplifies Polar Modulation
By Ken Gentile, Analog Devices ... Basic modulation mathematics and DDS (direct digital synthesis) provide designers with an all-digital technique for generating polar-encoded carrier signals. (EDN, 8/5/2004) -
Two DDS ICs Implement Amplitude-shift Keying
by Noel McNamara, Analog Devices, Inc. (EDN Design Idea, 12/25/2003) -
Integrated DDS Chip Takes Steps To 2.7 GHz
This highly integrated 2.7-GHz source includes all essential DDS circuitry along with a clock driver, divider, high-resolution DAC, and combination phase detector/charge pump. (ED Online, April 2004) -
DDS Circuit Generates Precise PWM Waveforms
by Colm Slattery, Analog Devices, Inc. (EDN, 10/2/2003) -
DDS IC Plus Frequency-To-Voltage Converter Make Low-Cost DAC
by Noel McNamara, Analog Devices, Inc. (EDN Design Idea, 2/5/2004) -
Simple Circuit Controls Stepper Motors
by Noel McNamara, Analog Devices, Inc. (EDN Design Idea, 1/8/04) -
Digital Potentiometers Vary Amplitude In DDS Devices
(Electronic Design, Ideas for Design, 5/29/2000) -
DDS Device Produces Sawtooth Waveform
Ramp or sawtooth waveforms are useful for a broad range of applications, including automatic-test equipment, benchtest equipment, and actuator control. (EDN Design Idea, 7/10/2003) -
400-MSample DDSs Run On Only +1.8 VDC
... This line of highly integrated DDS ICs features on-board RAM and crystal-oscillator circuitry to simplify the generation of agile and exotic waveforms. (Microwaves & RF Cover Story, 12/2002) -
AD9858: Flexible Integrated Synthesizer For Wireless
... The most important feature of the AD9858 is its ability to change frequency in less than 5 ns, meaning that there is virtually no application left where you will need to go the expense of switching between two separate synthesizers. (AnalogZone, RF/IF Zone Products for the Week of 9/23/2002) -
DDS Tackles BaseStations Head On
... This High-Performance, Low-Power Integrated Hybrid Synthesizer Flaunts A 10-b Digital-To-Analog Converter That Operates At Up To 1 GSample/s.
(Wireless Systems Design, September 2002) -
Video Portables and Cameras Get HDMI Outputs
By Doug Bartow, Analog Devices, Inc. -
Clock Requirements For Data Converters
(Electronic Design, 2/2005) -
DDS Design
By David Brandon, Analog Devices, Inc.
Direct digital synthesizers are known for their highly accurate digital tuning, low noise figure, and phase-continuous frequency-hopping capabilities, which make them more attractive than alternative analog frequency-synthesis solutions.
(EDN, 5/13/2004)
技術情報誌 Analog Dialogue (6)
- Analog Dialogue Vol.44 No.11 未発表論文から マルチチャンネルDDSで位相コヒーレントFSK変調 を実現
- Analog Dialogue Vol.44 No.1: 高速コンバータ・クロック分配デバイスの終端処理
-
Termination of High-Speed Converter Clock Distribution Devices
(The Back Burner, January 2010) -
Analog-to-Digital Converter Clock Optimization: A Test Engineering Perspective
(Analog Dialogue, Vol. 42, February 2008) -
Ask The Application Engineer—33: All About Direct Digital Synthesis
(Analog Dialogue, Vol. 38, August 2004) -
Single-Chip Clock Generator with 14-Channel Distribution Solves Timing Challenges in Networks
(Analog Dialogue, Volume 41, August, 2007)
データシート (64)
- AD9508: 1.65 GHz Clock Fanout Buffer with Output Dividers and Delay Adjust Data Sheet (Rev A, 04/2013) (pdf, 1422 kB)
- AD9525: Low Jitter Clock Generator with Eight LVPECL Outputs Data Sheet (Rev A, 04/2013) (pdf, 1296 kB)
- AD9512: 1.2 GHz Clock Distribution IC, 1.6 GHz Inputs, Dividers, Delay Adjust, Five Outputs Data Sheet (Rev A, 06/2005) (pdf, 960 kB)
- AD9577: Clock Generator with Dual PLLs, Spread Spectrum, and Margining Data Sheet (Rev 0, 10/2011) (pdf, 476 kB)
- AD9558: Quad Input Multiservice Line Card Adaptive Clock Translator with Frame Sync Data Sheet (Rev A, 04/2012) (pdf, 2329 kB)
- AD9557: Dual Input Multiservice Line Card Adaptive Clock Translator Data Sheet (Rev B, 05/2013) (pdf, 1299 kB)
- AD9523-1: Low Jitter Clock Generator with14 LVPECL/LVDS/HSTL/29 LVCMOS Outputs (Rev B, 03/2011) (pdf, 821 kB)
- AD9553: Flexible Clock Translator for GPON, Base Station, SONET/SDH, T1/E1, and Ethernet Data Sheet (Rev A, 10/2010) (pdf, 253 kB)
- AD9550: Integer-N Clock Translator for Wireline Communications (Rev 0, 09/2010) (pdf, 399 kB)
- AD9523: Jitter Cleaner and Clock Generator with 14 Differential or 29 LVCMOS Outputs Data Sheet (Rev C, 02/2013) (pdf, 690 kB)
- AD9524: Jitter Cleaner and Clock Generator with 6 Differential or 13 LVCMOS Outputs Data Sheet (Rev D, 02/2013) (pdf, 676 kB)
- ADCLK948: Two Selectable Inputs, 8 LVPECL Outputs, SiGe Clock Fanout Buffer Data Sheet (Rev A, 06/2010) (pdf, 709 kB)
- ADCLK950: Two Selectable Inputs, 10 LVPECL Outputs, SiGe Clock Fanout Buffer Data Sheet (Rev A, 06/2010) (pdf, 873 kB)
- ADCLK846: 1.8 V, 6 LVDS/12 CMOS Outputs Low Power Clock Fanout Buffer Data Sheet (Rev B, 05/2010) (pdf, 504 kB)
- ADCLK946: Six LVPECL Outputs,SiGe Clock Fanout Buffer Data Sheet (Rev A, 05/2010) (pdf, 470 kB)
- ADN4670: Programmable Low Voltage 1:10 LVDS Clock Driver (Rev A, 01/2012) (pdf, 164 kB)
- ADCLK944: 2.5 V/3.3 V, Four LVPECL Outputs,SiGe Clock Fanout Buffer (Rev 0, 03/2010) (pdf, 220 kB)
- AD9575: Network Clock Generator, Two Outputs Data Sheet (Rev A, 03/2010) (pdf, 309 kB)
- AD9571: Ethernet Clock Generator, 10 Clock Outputs (Rev 0, 09/2009) (pdf, 360 kB)
- AD9551: Multiservice Clock Generator Data Sheet (Rev B, 09/2009) (pdf, 726 kB)
- AD9572: Fiber Channel/Ethernet Clock Generator IC, PLL Core, Dividers, 7 Clock Outputs Data Sheet (Rev B, 04/2011) (pdf, 415 kB)
- AD9547: Dual/Quad Input Network Clock Generator/Synchronizer Data Sheet (Rev C, 02/2013) (pdf, 1753 kB)
- AD9573: PCI-Express Clock Generator IC, PLL Core, Dividers, Two Outputs Data Sheet (Rev 0, 07/2009) (pdf, 290 kB)
- ADCLK954: Two Selectable Inputs, 12 LVPECL Outputs, SiGe Clock Fanout Buffer Data Sheet (Rev A, 07/2009) (pdf, 354 kB)
- AD9548: Quad/Octal Input Network Clock Generator/Synchronizer Data Sheet (Rev C, 02/2013) (pdf, 1870 kB)
- ADCLK854: 1.8 V, 12-LVDS/24-CMOS Output, Low Power Clock Fanout Buffer Data Sheet (Rev 0, 04/2009) (pdf, 542 kB)
- AD9522-0: 2.8GHz VCO内蔵の12 LVDS/24 CMOS出力、クロック・ジェネレータ (Rev 0, 10/2008) (pdf, 4211 kB)
- AD9520-0: 2.8GHz VCO内蔵の12 LVPECL/24 CMOS出力、クロック・ジェネレータ (Rev 0, 09/2008) (pdf, 4220 kB)
- AD9516-5: 14-Output Clock Generator Data Sheet (Rev A, 08/2011) (pdf, 1625 kB)
- AD9522-5: 12 LVDS/24 CMOS Output Clock Generator Data Sheet (Rev 0, 12/2008) (pdf, 236 kB)
- AD9522-2: 12 LVDS/24 CMOS Output Clock Generator with Integrated 2.2 GHz VCO Data Sheet (Rev 0, 11/2008) (pdf, 239 kB)
- AD9522-1: 12 LVDS/24 CMOS Output Clock Generator with Integrated 2.4 GHz VCO Data Sheet (Rev 0, 11/2008) (pdf, 239 kB)
- ADCLK914: Ultrafast, SiGe, Open-Collector HVDS Clock/Data Buffer Data Sheet (Rev A, 10/2008) (pdf, 383 kB)
- AD9520-5: 12 LVPECL/24 CMOS Output Clock Generator Data Sheet (Rev 0, 10/2008) (pdf, 240 kB)
- AD9552: 発振器周波数アップコンバータ (Rev D, 07/2011) (pdf, 0)
- AD9522-4: 12 LVDS/24 CMOS Output Clock Generator with Integrated 1.6 GHz VCO Data Sheet (Rev 0, 10/2008) (pdf, 236 kB)
- AD9522-3: 12 LVDS/24 CMOS Output Clock Generator with Integrated 2 GHz VCO Data Sheet (Rev 0, 10/2008) (pdf, 239 kB)
- AD9520-2: 12 LVPECL/24 CMOS Output Clock Generator with Integrated 2.2 GHz VCO Data Sheet (Rev 0, 09/2008) (pdf, 1635 kB)
- AD9520-1: 12 LVPECL/24 CMOS Output Clock Generator with Integrated 2.5 GHz VCO Data Sheet (Rev 0, 09/2008) (pdf, 1636 kB)
- AD9510： クロック分配器、800MHz、PLL内蔵、分周器内蔵、遅延調整、8出力 (Rev A, 05/2006) (pdf, 806 kB)
- AD9520-3: 12 LVPECL/24 CMOS Output Clock Generator with Integrated 2 GHz VCO Data Sheet (Rev 0, 09/2008) (pdf, 1656 kB)
- AD9514：クロック分配IC、1.6GHz、分周器、遅延調整、3出力 (Rev 0, 06/2006) (pdf, 1472 kB)
- AD9520-4: 12 LVPECL/24 CMOS Output Clock Generator with Integrated 1.6 GHz VCO Data Sheet (Rev 0, 09/2008) (pdf, 1621 kB)
- AD9549: デュアル入力ネットワーク・クロック 発生器／同期化器 (Rev 0, 08/2007) (pdf, 979 kB)
- AD9518-3: 6-Output Clock Generator with Integrated 2.0 GHz VCO Data Sheet (Rev C, 01/2012) (pdf, 1091 kB)
- AD9518-2: 6-Output Clock Generator with Integrated 2.2 GHz VCO Data Sheet (Rev C, 01/2012) (pdf, 1385 kB)
- AD9518-4: 6-Output Clock Generator with Integrated 1.6 GHz VCO Data Sheet (Rev C, 01/2012) (pdf, 1072 kB)
- AD9518-1: 6-Output Clock Generator with Integrated 2.5 GHz VCO Data Sheet (Rev C, 01/2012) (pdf, 1373 kB)
- AD9518-0: 6-Output Clock Generator with Integrated 2.8 GHz VCO Data Sheet (Rev C, 01/2012) (pdf, 1382 kB)
- AD9517-3: 12-Output Clock Generator with Integrated 2.0 GHz VCO Data Sheet (Rev E, 03/2013) (pdf, 1192 kB)
- AD9517-2: 12-Output Clock Generator with Integrated 2.2 GHz VCO Data Sheet (Rev E, 03/2013) (pdf, 1181 kB)
- AD9517-4: 12-Output Clock Generator with Integrated 1.6 GHz VCO Data Sheet (Rev E, 03/2013) (pdf, 1188 kB)
- AD9517-1: 12-Output Clock Generator with Integrated 2.5 GHz VCO Data Sheet (Rev E, 03/2013) (pdf, 1178 kB)
- AD9517-0: 12-Output Clock Generator with Integrated 2.8 GHz VCO Data Sheet (Rev E, 03/2013) (pdf, 1831 kB)
- AD9516-3: 14-Output Clock Generator with Integrated 2.0 GHz VCO Data Sheet (Rev C, 02/2013) (pdf, 952 kB)
- AD9516-2: 14-Output Clock Generator with Integrated 2.2 GHz VCO Data Sheet (Rev C, 02/2013) (pdf, 940 kB)
- AD9516-4: 14-Output Clock Generator with Integrated 1.6 GHz VCO Data Sheet (Rev C, 02/2013) (pdf, 1859 kB)
- AD9516-1: 14-Output Clock Generator with Integrated 2.5 GHz VCO Data Sheet (Rev C, 02/2013) (pdf, 1808 kB)
- AD9515: 1.6 GHz Clock Distribution IC, Dividers, Delay Adjust, Two Outputs Data Sheet (Rev A, 04/2012) (pdf, 650 kB)
- AD9513: 800 MHz Clock Distribution IC, Dividers, Delay Adjust, Three Outputs Data Sheet (Rev 0, 09/2005) (pdf, 603 kB)
- AD9516-0: 2.8GHzのVCOを内蔵する14出力クロック・ジェネレータ (Rev 0, 04/2007) (pdf, 3207 kB)
- AD9540: 655 MHz Low Jitter Clock Generator Data Sheet (Rev A, 02/2006) (pdf, 839 kB)
- AD9511: 1.2 GHz Clock Distribution IC, PLL Core, Dividers, Delay Adjust, Five Outputs Data Sheet (Rev A, 06/2005) (pdf, 1187 kB)
- ADCLK905/ADCLK907/ADCLK925: 超高速SiGe ECLクロック／データ・バッファ (Rev 0, 08/2007) (pdf, 1000 kB)
設計ハンドブック (2)
-
High Speed System Applications
- Table of Contents (pdf, 2296 kB)
- Section 1: High Speed Data Conversion Overview (pdf)
- Section 2: Optimizing Data Converter Interfaces (pdf, 1677 kB)
- Section 3: DAC, DDS, PLL's, and Clock Distribution (pdf, 7676 kB)
- Section 4: PC Board Layout and Design Tools (pdf, 3570 kB)
-
High Speed Design Techniques
- Preface: High Speed Design Techniques (pdf, 94 kB)
- Section 1: High Speed Operational Amplifiers (pdf, 283 kB)
- Section 2: High Speed Op Amp Applications (pdf, 557 kB)
- Section 3: RF/IF Subsystems (pdf, 434 kB)
- Section 4: High Speed Sampling and High Speed ADCs (pdf, 335 kB)
- Section 5: High Speed ADC Applications (pdf, 398 kB)
- Section 6: High Speed DACs and DDS Systems (pdf, 253 kB)
- Section 7a: High Speed Hardware Design Techniques (pdf, 597 kB)
- Section 7b: Grounding in High Speed Systems (pdf, 655 kB)
FAQ（よくある質問） & RAQ（珍問／難問集） (122)
-
端数処理の衰退 — 有効桁数はどれだけ重要なのか？
Q: 測定データや算出データを記載するときには何桁の表示が必要でしょうか？ -
端数処理の衰退 — 有効桁数はどれだけ重要なのか？
Q: 測定データや算出データを記載するときには何桁の表示が必要でしょうか？ - 外形寸法図のBSCとは？
- Pwr Dissとは？
- ICの寿命や製品保証の資料は？
- 素子の成分表はありますか？
- My evaluation board is not working; the software is reporting a USB Communication Error. I verified that the evaluation board is connected to the PC and powered. What else can I check?
- クロックの設定ファイル
- デシケータ管理条件
- 使用温度の規定の見方は？
- Why do I see reference spurs?
- Why is my phase noise shape changing when I change the PLL settings?
- Why doesn't the PLL make my reference input and the clock outputs line up?
- How do I optimize my PLL loop for the best phase noise and/or jitter?
- My loop is not locking. How do I debug this?
- How long does it take for the PLL to lock?
- Help! My PLL came unlocked over temperature.
- How do I choose between active and passive filter in PLL loop?
- Should I reference the passive filter to ground? or supply?
- How do the PLLs in the AD951x parts compare to other ADI PLLs?
- How does the clock clean-up function of the AD951x parts work?
- Why do I want to run a fast PFD frequency?
- Is it ok for me to connect the same power supply to both the charge pump and distribution power supply pins?
- Why can't I use a bandpass filter for my loop filter?
- Should I tie my loop filter to ground or PLL supply?
- The loop filter was working great until I changed the divide ratio in PLL. What happened?
- How do I use a VCO with a supply greater than 5V?
- What suppliers do you recommend for VCO/VCXOs?
- Do VCXOs have better phase noise and jitter performance than VCOs?
- How do I know which VCO will work best with the AD9510?
- Is there an advantage to running a higher VCO frequency than the output frequency?
- How do I determine if a VCO is good enough for my purpose?
- Is there any difference between the nature of an oscillator's phase noise and the phase noise from a clock chip?
- Do different divide ratios cause variations in jitter?
- I have a clocking scheme which requires several different division ratios simultaneously. I have a frequency plan, but I'm concerned about crosstalk. How much of a problem is this with your clock distribution chips?
- Do divide ratios change the propagation delay?
- I want to use the phase offset feature on the AD9510 dividers to generate two signals 90° out of phase. How accurate is the phase offset?
- On the AD951x clock ICs, does the phase offset (coarse delay) affect the jitter?
- Why doesn't the mini-divider support the divide ratio I want?
- I want to use the variable delay adjust, but the jitter is too high. What can I do?
- I changed the coarse phase adjust in the evaluation software, but nothing happened. What's going on?
- What is the difference between the coarse phase adjust and the fine delay adjust?
- What is the fine delay adjust which is available on certain LVDS/CMOS outputs?
- Does the fine delay adjust affect the jitter?
- Why is the fine delay adjust not available on all the outputs?
- Is there a way to cause Input/Output rising edges to be synchronous (zero delay) with the AD9510/11?
- Will the AD9510 work without a reference input signal?
- What are the best clock sources for a distribution-only design?
- I am not using the CLK1 input on the AD9510. Can I just leave it floating?
- How good does my input signal need to be?
- I turned off my reference but the Digital Lock Detect (DLD) still says I'm locked.
- Can I shift the threshold on clocks for single-ended inputs?
- The reference input is differential, but my reference is single-ended. Do I need to convert to differential to drive the AD9510?
- Will differential or single-ended inputs/outputs improve my jitter?
- Why should I use differential rather than single-ended?
- How do I feed a single-ended signal into a differential input?
- Why do you recommend AC coupling, rather than DC coupling, at the clock inputs?
- Are the ADI clock parts stand-alone clock sources or do I still have to buy a clock source to drive these parts?
- Which provides better performance - a clock source with sinewave output, or one with differential square wave outputs?
- On the AD9510, what is the relationship between clock output jitter and CLK1/CLK2 input slew rate?
- I'm trying to write to the part in single-byte mode, but I can't write anything. What am I doing wrong?
- Can I use the 951X clocks to drive a mixer (RF LO)?
- My applications are RF, not for clocking data converters. Can ADI's 951X ICs be used for RF applications?
- I have an input present at the clock input, but I'm not seeing an output?
- What happens to the AD9510/11 clock outputs if the Reference Input (REFIN) signal goes away?
- What clock frequency comes out of the AD9510 outputs when you first apply power to the device?
- Is it possible to impedance match a clock output if it is heavily loaded? (e.g. CL=100pF)
- I ran the AD9510 outputs at 1.4 GHz and they seem to work fine. Is there a problem running them at 1.4 GHz?
- What should I do with unused channels on the AD9510?
- Can I tri-state the AD9510 outputs?
- On the AD9510, how can I make sure that the duty cycle of output clocks stays within 40% to 60% duty cycle window?
- What is the effect of distributing harmonically related clocks (on chip or on board) in terms of jitter?
- Is there any reason to use a transformer on a differential clock output to obtain a "clean" single-ended clock output?
- What are some of the advantages/disadvantages of using LVPECL vs. LVDS outputs?
- Does the AD9510 support 2.5V PECL?
- How much bandwidth is required to process a PECL or LVDS output?
- If I use only one of the PECL differential outputs and the unused output is terminated in 50Ω, how will this affect the phase noise or jitter of the single-ended output?
- If I change the level of PECL output, does it affect the jitter?
- What is the best way to terminate LVPECL outputs to get lowest jitter?
- Is it okay to AC-couple PECL or LVDS outputs?
- What is the fan-out capability of the CMOS, LVDS, and LVPECL outputs?
- What is the proper termination (value and location) for outputs?
- Are outputs short-circuit protected?
- Are the CMOS drivers on the clock devices complementary?
- Some of the schematics in the AD951x data sheets show an LVPECL termination scheme which is different from the classic termination often seen (50 Ω to Vs - 2V, or the Thevenin equivalent thereof). How does this work, and how did you chose 200 Ω for the resistors? Can I use 100 ohms to improve the slew rate (or jitter)?
- I have pulled SYNCB low, but I still have output from a channel. Why?
- Why can I not get the same output amplitude or rise and fall times as stated in your datasheet?
- The AD9510 datasheet says to use an external pull-up resistor on the FUNCTION pin. Why do I need this and what range of resistors will work?
- May I use the AD9540 for spread spectrum clocking?
- Can I get two clock outputs from the AD9540?
- What's the advantage of a DDS-based clock generator?
- Why does the AD9540 require special filtering on its analog output. What are the requirements of this filter?
- I'm working with optical networks - SONET/SDH. Do ADI's clock chips support these applications?
- On my board, I can't get the same low jitter numbers that are shown in the datasheet. Am I doing something wrong?
- How do you determine the bandwidth over which phase noise is integrated to obtain jitter?
- Using the "ADC SNR method", what is the equivalent bandwidth for the jitter specification?
- How do harmonic spurs in the output spectrum affect jitter (random or deterministic)?
- When a jitter number is specified without an associated bandwidth, what bandwidth should be assumed?
- How do you specify jitter?
- How do I use the clock part for jitter clean-up?
- If jitter can be calculated from phase noise measurements, is it possible to calculate phase noise from jitter numbers?
- Does jitter vary with different clock frequencies? How about phase noise?
- I sure can't measure jitter with femtosecond resolution on my scope! How do you do it? How much confidence do you have in the jitter figures that you are quoting for these parts?
- Do you guarantee performance shown in ADIsimCLK?
- Who do I contact for technical support on ADIsimCLK?
- Should I use the minimum charge pump current settings in order to minimize power?
- Can I run CMOS outputs at 5V?
- Can I use different power supply voltages for the PECL output drivers?
- Is .01 uF sufficient for power supply pin bypass?
- My application has pretty tight power consumption requirements. I am very interested in the capabilities of the AD9510, but I don't need every feature. Is it possible to turn off the unused features and save power?
- Why don't you spec psrr and cmrr in the datasheet?
- How do I get two AD951x (with PLL) to synchronize to the same reference input edge?
- I really need >10 clock outputs. Can I use multiple chips together and still guarantee that all output clocks are synchronized to REFIN?
- How do I synchronize multiple clock devices?
- What happens if I run the part in an ambient environment which exceeds 85°C?
- How can I determine the die temperature of your device?
- My circuit board has both an analog GND and a digital GND. How should I connect the AD9510 pins labeled GND?
- What PCB layout recommendations do you have for the of the exposed paddle on the bottom side of the LFCSP package?
-
間違えないで - 2乗平均平方根ですよ！
Q. 変動する信号をどうやって測定するのですか？ - Does Analog Devices offer a list of manufacturers of oscillators for DDS devices?
- Where can I find some good background material on direct digital synthesis?
- よくある質問（FAQ）: ダイレクト・デジタル・シンセサイザ（DDS）
メディア掲載一覧 (10)
- Support Components Can Make or Break Your Data Conversion Design
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RF Source Booklet
(pdf, 815 kB)
RF IC Product Overview - Version O (11/2012) - Tips for Improving High-Speed PCB Layout
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- Expanding Family of Integrated Clock ICs
- クロック＆タイミング
- Leading Inside Advertorials: Single-Chip Clock Generator with 14-Channel Distribution Solves Timing Challenges in Networks (pdf, 64 kB)
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Optical and High Speed Networking
(pdf, 2236 kB)
Analog Devices’ optical and high speed networking ICs solve a depth and breadth of challenges faced by today’s designers of datacom and telecom systems, optical modules, and subsystems. Analog Devices products address a wide range of networking applications from O/E/O conversion, clock recovery, and backplane transmission to monitoring and control of optical power, power management, and clock generation and distribution. -
Reset your thinking about clocks.
(pdf, 153 kB)
... In precision timing, analog is everywhere. - Clock and Timing ICs (pdf, 4970 kB)
関連記事 (11)
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Free Direct Digital Synthesis IC Evaluation Tool
(Control Engineering, 9/14/2006) -
Network Clock Synthesizer IC Provides, Maintains System Heartbeat Despite Adversity
(EE Product Center, 3/28/2007) -
14-Channel Clock ICs Boast Low Phase, Jitter
(Electronic Design, 10/23/2006) -
Circuit Simulation Tool Simplifies Clock Designs
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Where Analog Really Meets Digital
(EE Time, 8/29/2005) -
On-Line Evaluation Tool Simplifies Implementing DDS Semiconductors
(eeProductCenter, 8/16/2006) -
Clock Generator Beats 1-ps Jitter
(Microwaves & RF, 11/2006) -
Analog Devices Launches 14-Channel Clock Generator With 2.8 GHz VCO
(Fiber Optics Online, 10/23/2006) -
Ultra-low Jitter Performance Marks Analog Devices' Entry into the Clock IC Market
(eeProductCenter, 12/8/04) -
Clock-circuit-design Tool Recovers Engineer Time
(EDN, 8/23/2005) -
Low Jitter Clock Generator for Data Converters
... Analog Devices' first dedicated clocking product supporting the stringent needs of high performance data converters. (AVNET Technology Review, November 2004, Vol. 10, Issue 11)
参考文献 (2)
Seminars (1)
-
ADI Wireless Seminar 2006
- Index (pdf, 34 kB)
- Chapter I: Wireless Systems Overview (pdf, 212 kB)
- Chapter II: RF/IF Components and Specifications for Receivers (pdf, 642 kB)
- Chapter III: RF/IF Components and Specifications for Transmitters (pdf, 1379 kB)
- Chapter IV: RF Components Active and Passive Mixers (pdf, 480 kB)
- Chapter V: Phase Locked Loops for High Frequency Transmitters and Receivers (pdf, 469 kB)
- Chapter VI: A Detailed Look at Wireless Signal Chain Architectures (pdf, 380 kB)
- Chapter VII: Receiver Optimization Using Error Vector Magnitude Analysis (pdf, 189 kB)
- Chapter VIII: Design and Operation of Automatic Gain Control Loops for Receivers in Modern Communications Systems (pdf, 442 kB)
- Chapter IX: Using Calibration and Temperature Compensation to Improve RF Power Detector Accuracy (pdf, 285 kB)
- Chapter X: Measuring VSWR and Gain in Wireless Systems (pdf, 472 kB)
- Chapter XI: A 2.4-GHz Direct Conversion Transmitter for WiMAX and WiBro Applications (pdf, 275 kB)
- Chapter XII: Use a Wideband, Integer-N, PLL Synthesizer as a Direct 6-GHz Local Oscillator (pdf, 233 kB)
- Chapter XIII: Short Range Wireless Devices - Building a Global License-Free System at Frequencies Below 1GHz (pdf, 274 kB)
- Download All Chapters (zip, 5102 kB)
ソリューション・ブリテン (5)
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ADコンバータ／ドライバ IC ソリューション・ブリテン
ADコンバータ／ドライバ IC ソリューション・ブリテン, Volume 11, Issue 1 - RF IC ソリューション・ブリテン 2010年 No.5
- Analog-to-Digital Converter and Drivers ICs Solutions Bulletin, Volume 10, Issue 2 (pdf, 1358 kB)
- Digital-to-Analog Converter ICs Solutions Bulletin, Volume 10, Issue 1 (pdf, 1809 kB)
- D/AコンバータIC
技術資料 (1)
-
Analog-to-Digital Converter Clock Optimization: A Test Engineering Perspective
(pdf, 909 kB)
By Rob Reeder, Wayne Green, and Robert Shillito
ユーザー・ガイド (22)
- UG-485: Evaluation Board for the ADF4153A Fractional-N PLL Frequency Synthesizer (pdf, 672 kB)
- UG-406: Evaluation Board for the ADF4150HV PLL Frequency Synthesizer (pdf, 1457 kB)
- UG-380: Evaluation Board for the ADF4150 PLL Frequency Synthesizer (pdf, 1940 kB)
- UG-369: Evaluation Board for the ADF4151 PLL Frequency Synthesizer (pdf, 1494 kB)
- UG-203: Evaluating the AD9550 Integer-N Clock Translator (pdf, 201 kB)
- UG-182: Evaluation Board User Guide for AD9523-1 Clock Generator (pdf, 711 kB)
- UG-169: Evaluating the AD9523/AD9524 Clock Generator (pdf, 608 kB)
- UG-125: Setting Up the Evaluation Board for the ADCLK944 (pdf, 171 kB)
- UG-093: Evaluation Board User Guide for the Dual, Continuous Time Sigma-Delta Modulator (pdf, 1449 kB)
- UG-035: Evaluating the AD9552 Oscillator Frequency Upconverter (pdf, 522 kB)
-
Evaluation Software Documentation
-
UG-076: AD9520-x Evaluation Board User Guide
(pdf, 1047 kB)
These instructions are for the setup and operation of the AD9520 evaluation board and software.
-
UG-076: AD9520-x Evaluation Board User Guide
(pdf, 1047 kB)
-
UG-075: AD9516-x, AD9517-x, and AD9518-x Evaluation Board User Guide
(pdf, 1089 kB)
This user guide covers installation and operation of the AD9516/17/18 evaluation board and software. -
Evaluation Software Documentation
-
UG-077: AD9522-x Evaluation Board User Guide
(pdf, 927 kB)
This User Guide covers the setup and operation of the AD9522 Evaluation Board.
-
UG-077: AD9522-x Evaluation Board User Guide
(pdf, 927 kB)
-
UG-071 Evaluation Board User Guide
(pdf, 202 kB)
Setting Up the Evaluation Board for the ADCLK846 -
UG-070 Evaluation Board User Guide
(pdf, 217 kB)
Setting Up the Evaluation Board for the ADCLK854 - UG-069: Setting Up the Evaluation Board for the ADCLK946 (pdf, 196 kB)
- UG-066: Setting Up the Evaluation Board for the ADCLK954 (pdf, 230 kB)
- UG-068: Setting Up the Evaluation Board for the ADCLK948 (pdf, 211 kB)
- UG-067: Setting Up the Evaluation Board for the ADCLK950 (pdf, 217 kB)
- UG-058: Setting Up the Evaluation Board for the ADCLK914 (pdf, 305 kB)
- UG-006: Setting Up the Evaluation Board for the ADCLK905/ADCLK907/ADCLK925 (pdf, 335 kB)
-
UG-002: Evaluation Board User Guide
(pdf, 944 kB)
Evaluating the AD9551 Multiservice Clock Generator
