| Chapter: N/A | Page: 13 |
| DOC ID: DOC-451 | |
| Change | |
| In Table 4 (DMOVLAY Bits), the A12:0 entries for External Overlay 1 and 2 are incorrect. In both instances Change from: "13 LSBs of Address Between 0x2000 and 0x3FFF" Change to: "13 LSBs of Address Between 0x0000 and 0x1FFF" | |
| Chapter: N/A | Page: 13 |
| DOC ID: DOC-441 | |
| Change | |
| In Table 4 (DMOVLAY Bits), the A12:0 entries for External Overlay 1 and 2 are incorrect. In both instances. Change from: "13 LSBs of Address Between 0x2000 and 0x3FFF" Change to: "13 LSBs of Address Between 0x0000 and 0x1FFF" | |
| Chapter: N/A | Page: 15 |
| DOC ID: DOC-445 | |
| Change | |
| In Figure 10 (IDMA Control/OVLAY Registers), the description of bit 14 (SHORT READ ONLY) in the IDMA OVERLAY register is incorrect. The correct definition of bit 14 is: 1 = enable Short Read Only 0 = disable Short Read Only | |
| Chapter: N/A | Page: 40 |
| DOC ID: DOC-587 | |
| Change | |
In the outline dimensions figure, the remove following (or similarly worded) note:
THE ACTUAL POSITION OF EACH BALL IS WITHIN ... mm OF ITS IDEAL POSITION RELATIVE TO THE BALL GRID. | |
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