トピック
- 2009年10月27日 通信機器、携帯機器、計測機器、ヘルスケア機器向けに26種の高速A/Dコンバータを一挙投入
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2009年10月13日
RAQ（珍問／難問集）
Q. アナログ入力がグランディング（接地）されているのに、なぜ出力でもグランドが必要なのでしょうか？ - 2009年09月15日 アナログ・デバイセズ株式会社、データ・コンバータ基礎技術の日本語オンライン・セミナーを開始
新製品
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AD7194- 8-Channel, 4.8 kHz, Ultralow Noise, 24-Bit Sigma-Delta ADC with PGA
The AD7194 is a low noise, complete analog front end for high precision measurement applications. It contains a low noise, 24-bit sigma-delta (Σ-Δ) analog-to-digital converter (ADC). The on-chip low noise gain stage means that signals of small amplitude can interface directly to the ADC. The device can be configured to have eight differential inputs or sixteen pseudo differential inputs. The 続きを見る
データシート Rev 0, 11/2009 (pdf 996kB)
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AD7985- 16-Bit, 2.5 MSPS PulSAR 11 mW ADC in QFN
The AD7985 is a 16-bit, 2.5 MSPS successive approximation analog-to-digital converter (SAR ADC). It contains a low power, high speed, 16-bit sampling ADC, an internal conversion clock, an internal reference (and buffer), error correction circuits, and a versatile serial interface port. On the rising edge of CNV, the AD7985 samples an analog input, IN+, between 0 V and REF with respect to a ground 続きを見る
データシート Rev 0, 09/2009 (pdf 656kB)
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AD9277- Octal LNA/VGA/AAF/14-Bit ADC and CW I/Q Demodulator
The AD9277 is designed for low cost, low power, small size, and ease of use. It contains eight channels of a variable gain amplifier (VGA) with a low noise preamplifier (LNA); an anti-aliasing filter (AAF); a 14-bit, 10 MSPS to 50 MSPS analog-to-digital converter (ADC); and an I/Q demodulator with programmable phase rotation.
Each channel features a variable gain range of 42 dB, a fully 続きを見る
データシート Rev 0, 08/2009 (pdf 979kB)
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AD9251- 14-Bit, 20 MSPS/40 MSPS/65 MSPS/80 MSPS, 1.8 V Dual Analog-to-Digital Converter
The AD9251 is a monolithic, dual-channel, 1.8 V supply, 14-bit, 20 MSPS/40 MSPS/65 MSPS/80 MSPS analog-to-digital converter (ADC). It features a high performance sample-and-hold circuit and on-chip voltage reference.
The product uses multistage differential pipeline architecture with output error correction logic to provide 14-bit accuracy at 80 MSPS data rates and to guarantee no missing 続きを見る
データシート Rev A, 11/2009 (pdf 789kB)
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