This circuit uses the ADL5534 IF amplifier to provide a dual IF gain block for the AD9640 14-bit, 150 MSPS dual ADC. The ADL5534 is a high linearity, dual fixed, 20 dB gain amplifier that can be adapted for use as a driver for a high performance IF sampling ADC. The ADL5534 provides a simple approach to interfacing the RFIN signal level of 200 mV p-p to the 2 V p-p full scale of the high speed ADC. The low noise (2.5 dB NF at 70 MHz) and low distortion (IP3 of 40 dBm at 70 MHz) of the ADL5534 ensure that the ADC performance is not compromised.

Figure 1 shows an application circuit where the ADL5534 drives the AD9640, a 150 MSPS, 14-bit ADC. The two 49.9 Ω resistors connected to the AD9640 CML output establish the 0.9 V dc bias for the AD9640 inputs and set the AD9640 differential input impedance to 100 Ω.

When operated as a quasi-differential amplifier, the ADL5534’s two amplifiers present 100 Ω differential input and output impedances. The input signal from a 50 Ω RF source is converted to a differential signal with a 1:2 impedance ratio flux-coupled transformer. This matches the 50 Ω source to the 100 Ω differential load of the ADL5534. Between the ADL5534 output and the AD9640 input, a third-order low-pass filter presenting a 100 Ω differential impedance to the source and load is implemented.

Due to the different common mode voltage levels required by the ADL5534 and the AD9640, the ADL5534 must be ac-coupled to the AD9640. Capacitors of 100 pF were chosen to reduce any low frequency noise coming from the ADL5534 and to provide dc blocking.

The measured results for this filter show 0.5 dB insertion loss for a 20 MHz bandwidth centered around 92 MHz. Figure 2 shows the measured wideband response for the filter.

The single-tone FFT results shown in Figure 3 for an input signal of approximately 93 MHz show an SNR of 69.3 dB and an SFDR of 82 dBc. Note that because of aliasing, the fundamental frequency in the FFT is at 122.8 MHz – 93 MHz = 31.8 MHz.

The two-tone results for tones at 91 MHz and 93 MHz are shown in Figure 4 and yield an IMD3 of −80.5 dBc and SFDR of 78 dBc. The AD9640 was clocked at a sample rate of 122.8 MSPS for both single and two-tone tests.

This application circuit can be modified for any IF frequency within the operating range of the ADL5534 and AD9640. As an alternative to the ADL5534, the AD8375, a digitally programmable differential variable gain amplifier, can be used.

Alternatively, the AD8352, a resistor programmable differential amplifier, can be used to convert from single ended to differential without the requirement of an external balun. The AD8352, AD8375, and AD8376 (dual version of the AD8375) are all true differential amplifiers that provide rejection of common-mode signals at their input.

The circuit must be constructed on a multilayer PC board with a large area ground plane. Proper layout, grounding, and decoupling techniques must be used to achieve optimum performance (see MT-031 Tutorial, MT-101 Tutorial, the ADL5534 evaluation board layout, and the AD9640 evaluation board layout). Both the ADL5534 and the AD9640 have exposed thermal pads that should be soldered directly to the low impedance ground plane.