The circuit described in this document provides a dc-coupled, single-ended-to-differential conversion of a bipolar input signal to the AD7352 dual, 3 MSPS, 12-bit SAR ADC. This circuit is designed to ensure maximum performance of the AD7352 by providing adequate settling time and low impedance.

Differential operation requires V_INx+ and V_INx− of the ADC to be driven simultaneously with two equal signals that are 180° out of phase and are centered around the proper common-mode voltage. Because not all applications have a signal preconditioned for differential operation, there is often a need to perform a single-ended-to-differential conversion. An ideal method of applying differential drive to the AD7352 is to use a differential amplifier such as the AD8138. This part can be used as a single-ended-to-differential amplifier or as a differential-to-differential amplifier. The AD8138 also provides common-mode level shifting. Figure 1 shows how the AD8138 can be used as a single-ended-to-differential amplifier in a dc-coupled application. The positive and negative outputs of the AD8138 are connected to the respective inputs on the ADC through a pair of series resistors to minimize the loading effects of the switched capacitor inputs of the ADC. The architecture of the AD8138 results in outputs that are very highly balanced over a wide frequency range without requiring tightly matched external components. The single-ended-to-differential gain of the circuit in Figure 1 is equal to R_F/R_G, where R_F = R_F1 = R_F2 and R_G = R_G1 = R_G2.

If the analog inputs source being used has zero impedance, all four resistors (R_G1, R_G2, R_F1, and R_F2) should be the same as shown in Figure 1. If the source has a 50 Ω impedance and a 50 Ω termination, for example, the value of R_G2 should be increased by 25 Ω to balance this parallel impedance on the input and thus ensure that both the positive and negative analog inputs have the same gain. This also requires a small increase in R_F1 and R_F2 to compensate for the gain loss caused by increasing R_G1 and R_G2. Complete analysis for the terminated source condition is found in the ADIsimDiffAmp interactive design tool and in MT-076 Tutorial.

The AD7352 requires a driver that has a very fast settling time due to the very short acquisition time required to achieve 3 MSPS throughput with a serial interface. The track-and-hold amplifier on the front end of the AD7352 enters track mode on the rising edge of the 13th SCLK period during a conversion. The ADC driver must settle before the track-and-hold returns to hold (68 ns later for 3 MSPS throughput on the AD7352 using a 48 MHz SCLK). The AD8138 has a specified 16 ns settling time that satisfies this requirement.

The voltage applied to the V_OCM pin of the AD8138 sets up the common-mode voltage. In Figure 1, V_OCM is connected to 1.024 V, which is a divided version of the internal 2.048 V reference on the AD7352. If the on-chip 2.048 V reference on the AD7352 is to be used elsewhere in a system (as illustrated in Figure 1), the output from REF_A or REF_B must first be buffered. The OP177 features the highest precision performance of any op amp currently available and is a perfect choice for a reference buffer.

Note that the AD8138 operates on dual 5 V supplies whereas the AD7352 is specified for power supply voltages of 2.5 V to 3.6 V. Care must be taken to ensure that the input maximum input voltage limits of the AD7352 are not exceeded during transient or power-on conditions (see MT-036 Tutorial). In addition, the circuit must be constructed on a multilayer PC board with a large area ground plane. Proper layout, grounding, and decoupling techniques must be used to achieve optimum performance (see MT-031 Tutorial, MT-101 Tutorial, and the AD7352 evaluation board layout).

The OP07D, an ultralow offset voltage op amp, is a lower cost alternative to the OP177. It offers similar performance with the exception of the offset voltage specification. Alternatively, the AD8628 or the AD8638 offers very high precision with very low drift with time and temperature.