The circuit described in this document provides single-ended to differential conversion of an input signal to the AD7352 dual, 3MSPS, 12-bit SAR ADC. This circuit has been designed to ensure maximum performance of the AD7352 by providing adequate settling time and low impedance.

Differential operation requires VIN+ and VIN− to be driven simultaneously with two equal signals that are 180° out of phase. Because not all applications have a signal preconditioned for differential operation, there is often a need to perform a single-ended-to-differential conversion. An ideal method of applying differential drive to the AD7352 is to use a differential amplifier such as the AD8138. This part can be used as a single-ended-to-differential amplifier or as a differential-to-differential amplifier. The AD8138 also provides common-mode level shifting. Figure 1 shows how the AD8138 can be used as a single-ended-to-differential amplifier. The positive and negative outputs of the AD8138 are connected to the respective inputs on the ADC via a pair of series resistors to minimize the effects of switched capacitance on the front end of the ADC. The architecture of the AD8138 results in outputs that are very highly balanced over a wide frequency range without requiring tightly matched external components.

If the analog inputs source being used has zero impedance, all four resistors (RG1, RG2, RF1, and RF2) should be the same. If the source has a 50 Ω impedance and a 50 Ω termination, for example, the value of RG2 should be increased by 25 Ω to balance this parallel impedance on the input and thus ensure that both the positive and negative analog inputs have the same gain. The outputs of the amplifier are perfectly matched balanced differential outputs of identical amplitude and are exactly 180° out of phase.

The AD7352 requires a driver that has a very fast settling time due to the very short acquisition time required in order to achieve 3MSPS throughput with a serial interface. The track and hold amplifier on the front end of the AD7352 enters track mode on the rising edge of the 13th SCLK period during a conversion. The ADC driver must settle before the track and hold returns to hold (68 ns later for 3MSPS throughput on the AD7352 using a 48MHz SCLK). The AD8138 has a specified 16ns settling time which satisfies this requirement.

The voltage applied to the VOCM pin of the AD8138 sets up the common-mode voltage. In figure 1, VOCM is connected to 1.024V which is a divided down version of the internal reference on the AD7352. If the on-chip 2.048V reference on the AD7352 is to be used elsewhere in a system, (as illustrated in Figure 1) the output from REFA or REFB must first be buffered. The OP177 features the highest precision performance of any op amp currently available, and is a perfect choice for a reference buffer.

The OP07D, an ultra-low offset voltage op-amp, is a lower cost alternative to the OP177. It offers similar performance with the exception of the Vos specification. Alternatively, the AD8628 or the AD8638 offer very high precision with very low drift with time and temperature.