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JEDEC JESD204A (2008) is an industry standard for the serial digital interconnection of a DAC or an ADC to a logic device. It supports the concept of multiple synchronously bonded serial data lanes which enhances its use in I/Q sampling systems. Although JESD204A standard limits the lane speed to 3.125 Gbps, the new “B” standard pushes that limit to 12.5 Gbps
Unwanted variations in the frequency or phase of a digital or analog signal.
Clock Jitter is the variation in time of the sampling edge of the clock signal. Clock Jitter can become a limiting factor in achievable SNR at Intermediate Frequencies.