Uncompromised Clocking Solution for 16-Bit 2.5Gsps High Performance DAC

Design Note 555: Introduction

The LTC2000 16-bit 2.5Gsps DAC offers excellent AC performance. For many DAC applications, phase noise, noise spectral density (NSD), and spurious free dynamic range (SFDR) are critical to maximize the number of possible channels in a band without eroding the signal to noise ratio (SNR) in the band of interest. High speed DACs require a clean sample clock to achieve the best possible noise and spurious performance. Using the ultralow noise and spurious LTC6946 PLL synthesizer as a clock source for the LTC2000 maximizes system performance (Figure 1).

Figure 1. LTC6946 Driving the LTC2000

Figure 1. LTC6946 Driving the LTC2000

16-Bit High Speed DAC

The high spectral purity and low noise of the LTC2000 make it an excellent signal generator. Figure 2 highlights the excellent additive phase noise performance of the LTC2000 of –165dBc/Hz at 1MHz offset and –147dBc/Hz at 10kHz offset with a 65MHz output. For output frequencies up to 100MHz, the LTC2000 has NSD better than –166dBm/Hz and SFDR better than 76dB. For higher output frequencies up to 1GHz, the SFDR is more than 68dB and the NSD remains below –155dBm/Hz. Producing these results requires a clock with good noise, high spectral purity and excellent jitter performance.

Frequency Synthesizer as a Clock Source

The LTC6946 is an integer-N frequency synthesizer with integrated VCO that can produce signals from 370MHz up to 6.39GHz. It features excellent phase noise performance and very low spurious content, making it ideal to clock the LTC2000 at 2.5GHz. It can drive the LTC2000 directly without filtering to produce a spectrally pure low noise output.

The LTC2000 divides the clock frequency (fCLK) down to an output frequency (fOUT). This frequency division causes the phase noise of the clock to appear at the DAC output, attenuated by a factor of 20 • log(fCLK/ fOUT). The total phase noise at the DAC output will be a combination of the additive phase noise of the LTC2000 (Figure 2) and the attenuated phase noise of the LTC6946.

Figure 2. Additive Phase Noise of the LTC2000, fOUT = 65MHz, fDAC = 2.5GHz

Figure 2. Additive Phase Noise of the LTC2000, fOUT = 65MHz, fDAC = 2.5GHz

Wideband phase noise or jitter on the sample clock must be minimized to avoid degrading the NSD of the DAC output, and the low spurious content of the LTC6946 output is critical to maintain high SFDR at the output of the LTC2000.

The lower the phase noise, the closer signals generated by the LTC2000 can be spaced. This allows more information to be transmitted in a given bandwidth. With a lower phase noise floor, the total SNR of the system increases, which improves the integrity of the signal produced by the LTC2000.

Results

The single-sideband phase noise of the LTC2000 clocked by the LTC6946 is shown in Figure 3. The LTC6946 works well with the LTC2000, producing a clean clock that maximizes the DAC’s performance. The combination of the LTC2000 and the LTC6946 offer phase noise and spurious performance comparable to the best signal generators.

Figure 3. Phase Noise of the LTC2000 Output at 80MHz Clocked by the LTC6946-3

Figure 3. Phase Noise of the LTC2000 Output at 80MHz Clocked by the LTC6946-3

Author

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Clarence Mayott

Clarence Mayott is a mixed signal application section leader with over 10 years of experience at Linear Technology.

Beginning with the DC1151, a demo board for the LTC2246H, Clarence has designed nearly all of the high speed ADC demo boards for Linear Technology. These boards have been used for evaluation purposes in a wide range of applications. He designed demo boards with complete signal chains combining amplifiers and ADC combinations to help the end customer evaluate systems more easily. He also designed companion boards, including clock and signal source boards, to help facilitate the evaluation of high speed ADC demo boards. Clarence manages the continued development of PScope, the software used for various pipeline and SAR ADCs.

His expertise in design and layout of demo boards allows him to instruct customers on how to implement high speed ADCs into their own designs. He has worked on many technical areas, including medical, automotive and communications. His experience allows him to see schematic errors, minute layout errors, and other design flaws in designs.

With the release of the LTC2000, Clarence has expanded his knowledge base to include high speed DACs and waveform generation in addition to high speed ADCs. As an application section leader he oversees the continued development of LTDACGen a new software tool for generating complex waveforms for high speed DACs.

He has given technical trainings both within Linear Technology and to potential customers describing how to implement proper signal chains from the antenna through the FPGA.

He received an M.S. in Electrical Engineering from Santa Clara University and a B.S. degree in Electrical Engineering from California State University Polytechnic San Luis Obispo.