High Speed Converters: An Overview of What, Why, and How

As the gateway between the “real world” analog domain and the digital world of 1s and 0s, data converters are a critical element of modern signal processing. Over the past three decades, numerous innovations in data conversion have not only allowed performance and architecture advances in everything from medical imaging to cellular communications to consumer audio and video, they have helped to create entirely new applications.

The continuing expansion of broadband communications and high performance imaging applications has put a particular emphasis on high speed data conversion: converters capable of handling signals with bandwidths of 10 MHz to more than 1 GHz. A variety of converter architectures are being used to reach these higher speeds, each with special advantages. Moving back and forth between the analog and digital domain at high speeds also presents some special challenges in signal integrity—not just for the analog signal, but for clock and data signals as well. Understanding these issues is important not just in component selection, but can even impact the choice of overall system architecture.

Figure 1.

Faster, Faster, Faster

In many technology domains, we have come to associate technology advances with greater speeds: data communications, from Ethernet to wireless LAN to cellular, is all about moving bits faster. Microprocessors, digital signal processors, and FPGAs advance substantially through advances in clock rates. They are primarily enabled by shrinking process lithographies, which provide smaller transistors that can switch faster (and at lower power). These dynamics have created an environment of exponentially expanding processing power and data bandwidth. These powerful digital engines create an exponentially increasing appetite for signals and data to be crunched: from still images, to video, to broadband spectrum, be it wired or wireless. A processor running at 100 MHz might be able to effectively manipulate signals with 1 MHz to 10 MHz of bandwidth: processors running at multiple GHz clock rates can handle signals with bandwidths of hundreds of MHz.

The greater processing power and speed leads naturally to faster data conversion: broadband signals expand their bandwidths (often to the spectrum limits set by physics or regulators), imaging systems look to handle more pixels per second to process higher resolution images faster. Systems are being rearchitected to take advantage of this extreme processing horsepower, including a trend toward parallel processing, which may mean multichannel data converters.

Another important architectural change is the trend toward multicarrier/multichannel, or even software-defined systems. Conventional, analog intensive systems do much of the signal conditioning work (filtering, amplification, frequency translation) in the analog domain; the signal is taken digital after it has been carefully prepared. An example of this would be an FM radio: a given radio station will be a 200 kHz wide channel sitting somewhere in the 88 MHz to 108 MHz FM radio band. A conventional receiver will frequency translate the station of interest to a 10.7 MHz intermediate frequency, filter out all the other channels, and amplify the signal to the optimal amplitude for demodulation. A multicarrier architecture digitizes the entire 20 MHz FM band, and digital processing is used to select and recover the radio stations of interest. While the multicarrier scheme requires much more sophisticated circuitry, it offers some great system advantages: the system can recover multiple stations simultaneously, including side band stations. If properly designed, a multicarrier system can even be software reconfigured to support new standards (for example, the new HD radio stations that have been placed in radio side bands). The ultimate extension of this approach is to have a wideband digitizer that can take in all the bands, and a powerful processor that can recover any sort of signal: this is referred to as a software-defined radio. There are equivalent architectures in other fields—software-defined instrument, software-defined cameras, etc. One can think of this as the signal processing equivalent of virtualization. The enabling hardware for these sorts of flexible architectures is powerful digital processing, and high speed, high performance data conversion.

Figure 2. Example of multiple carrier

Bandwidth and Dynamic Range

The fundamental dimensions of signal processing, whether analog or digital, are bandwidth and dynamic range—these two factors determine how much information a system can actually handle. For communications, Claude Shannon’s theorem uses these two dimensions to describe the fundamental theoretical limit of how much information can be carried in a communications channel, but the principles apply across a variety of regimes. For an imaging system, the bandwidth determines how many pixels can be processed in a given amount of time, and the dynamic range determines the intensity or color range between the dimmest perceptible light source and the point at which the pixel saturates.

Figure 3. The fundamental dimensions of signal processing

The useable bandwidth of a data converter has a fundamental theoretical limit set by the Nyquist sampling theorem—to represent or handle a signal with bandwidth F, one needs a data converter running at a sample rate of at least 2 F (note that this law applies for any sampled data system—be it analog or digital). For practical systems, some amount of oversampling simplifies the system design substantially, so a factor of 2.5× to 3× the signal bandwidth is more typical. As noted earlier, the continually increasing processing power increases a system’s ability to handle greater bandwidths, and system trends in cellular telephony, cable systems, wired and wireless LAN, image processing, and instrumentation are moving to more broadband systems. This increasing appetite for bandwidth demands higher sample rates from the data converters.

If the bandwidth dimension is intuitively clear, the dynamic range dimension may be a bit less obvious. In signal processing, the dynamic range represents the spread between the largest signal the system can handle without suturing or clipping, and the smallest signal that the system can effectively capture. One can consider two types of dynamic range: floating point dynamic range could be realized with a programmable gain amplifier (PGA) in front of a low resolution analog-to-digital converter (ADC) (imagine four bits of PGA in front of an 8-bit converter for 12 bits of floating point dynamic range): with the gain set low, this arrangement can capture large signals without over-ranging the converter. When the signal is very small, the PGA can be set for high gain to amplify the signal above the converter’s noise floor. The signal could be a strong or weak radio station, or a bright or dim pixel in an imaging system. This sort of floating point dynamic range can be very effective for conventional signal processing architectures that are only trying to recover one signal at a time. 

Instantaneous dynamic range is more powerful: in this arrangement, the system has sufficient dynamic range to simultaneously capture the large signal without clipping and still recover the small signal—now we may need a 14-bit converter. This principle applies across a number of applications—recovering both a strong and weak radio station or cell phone call signal, or a very bright and very dim section of one image. As systems want to move to more sophisticated signal processing algorithms, there is a tendency toward needing more dynamic range. This allows the system to handle more signals—if all signals are the same strength, and you need to process twice as many signals, then you would need 3 dB more dynamic range (all other things being equal). Perhaps more importantly, as noted previously, if the system needs to handle both strong and weak signals simultaneously, the increase in dynamic range requirements can be much more dramatic.

Different Measures for Dynamic Range

In digital signal processing, the key parameter for dynamic range is the number of bits in the representation of the signal, or word length: a 32-bit processor has more dynamic range than a 16-bit processor. Signals that are too large are clipped—a highly nonlinear operation that destroys the integrity of most signals. Signals that are too small—less than 1 LSB in amplitude—become undetectable, and are lost. This finite resolution is often referred to as quantization error, or quantization noise, and can be one important factor in establishing the floor of detectability.

Quantization noise is also a factor in mixed-signal systems, but there are a number of factors that can determine the useable dynamic range in data converters, each with its own specification:

  • Signal-to-noise ratio (SNR)—the ratio of the full scale of the converter to the total noise in the band. This noise could come from quantization noise (as described above), thermal noise (present in all real world systems), or other error terms (such as jitter).
  • Static nonlinearity—differential nonlinearity. (DNL), and integral nonlinearity (INL)—measures the nonidealities of the dc transfer function from input to output of the data converter (DNL often establishes the dynamic range of an imaging system).
  • Total harmonic distortion—static and dynamic nonlinearities produce harmonic tones, which can effectively mask other signals. THD frequently limits the effective dynamic range of audio systems
  • Spurious-free dynamic range (SFDR)—considers the highest spectral spur, whether it be a second or third harmonic clock feedthrough, or even 60 Hz hum, compared to the input signal. Since the spectral tones, or spurs, can mask small signals, SFDR is a good representation of useable dynamic range in many communications systems.

There are other specifications out there—in fact, each application may have its own effective description of dynamic range. The resolution of the data converter is a good first proxy for its dynamic range, but choosing the right specification as the true determination is very important. The key principle is that more is better. While many systems immediately recognize the need for greater bandwidth in their signal processing, the implications for dynamic range may be less obvious, but even more demanding.

It’s worth noting that while bandwidth and dynamic range are the two primary dimensions of signal processing, it’s useful to think about a third dimension of efficiency: this helps us get at the question of “How much will the extra performance cost me?” We can think of cost in terms of purchase price, but a more technically pure way of weight cost for data converters and other electronic signal processing is in terms of power consumption. Higher performance systems—those with more bandwidth or more dynamic range—tend to consume more power. As technology advances, we are looking to push bandwidth and dynamic range up and power consumption down. 

Key Applications

As just described, each application will have different requirements in terms of fundamental signal dimensions, and within a given application there can be a wide range of performance. Consider a 1 Megapixel camera vs. a 10 Megapixel camera, for example. Figure 4 provides a representative illustration of the bandwidth and dynamic range typically required in some different applications. The upper half of this chart will often be characterized as high speed—converters with sampling rates of 25 MHz and greater, that can effectively handle bandwidths of 10 MHz or more.

Figure 4. Some typical applications plotted to show their requirements in terms of bandwidth (speed) and dynamic range (bits of resolution)

It’s worth noting that this applications picture is not static. Existing applications can take advantage of new, higher performance technologies to increase their capabilities—high definition camcorders, or higher resolution 3D ultrasound machines, for example. There are also entirely new applications emerging each year—and much of the new activity will be at the outer edge of the performance frontier: enabled by new combinations of high speed and high resolution. This creates an expanding edge of converter performance, like a ripple in a pond.

It’s also important to keep in mind that most applications are concerned about power consumption: for portable/battery-powered applications, power consumption may be the primary technical constraint, but even line powered systems are finding that the power consumption of the signal processing elements (be they analog or digital) are ultimately limiting how much the system can accomplish in a given physical area.

Technology Trends and Innovation—How We're Getting There . . .

Given this applications pull for increasing high speed data converter performance, the industry has responded with continuing advances in the technology. The technology push for advanced high speed data converters comes from several factors: 

  • Process technologies: Moore’s Law and data converters—the semiconductor industry has a remarkable track record for continuously advancing digital processing horsepower, substantially driven by advances in wafer processing to ever finer lithographies. Deep submicron CMOS transistors have much greater switching speeds than their predecessors, enabling controllers, digital processors, and FPGAs to clock at multi-GHz speeds. Mixed-signal circuits like data converters can also take advantage of these lithography advances and “ride Moore’s Law” to higher speeds—but for mixed-signal circuits, there is a penalty: the more advanced lithography processes tend to operate at increasingly lower supply voltages. This means smaller signal swings in analog circuits, making it more difficult to maintain analog signals above the thermal noise floor: one gets increased speed at the price of reduced dynamic range.
  • Advanced architectures (this is not your grandmother’s data converter)—complementing the advances in semiconductor processes, the last 20 years have seen several waves of innovation in high speed data converter architectures that are helping to realize greater bandwidths and greater dynamic range with remarkable power efficiency. There are a variety of approaches that are traditionally used for high speed analog-to-digital converters, including flash, folding, interleaved, and pipeline, and these continue to be very popular. They have been joined by architectures that are more traditionally associated with lower speed applications, including successive approximation register (SAR), and ∆-∑, that have been creatively adapted to high speed use. Each architecture offers its own set of advantages and disadvantages: certain applications will tend to find favorite architectures based on these trade-offs. For high speed DACs, the architecture of choice tends to be switched current mode structures, though there are many variants of these, and switched capacitor approaches have been steadily increasing their speeds, and are still particularly popular in some embedded high speed applications.
  • Digitally assisted approaches—in addition to process and architecture, there has also been quite a bit of innovation in circuit techniques for high speed data converters over the years. Calibration approaches have been around for decades, and have been critically important in compensating the element mismatch inherent in integrated circuits and allowing circuits to reach to higher dynamic range. Calibration has moved beyond the domain of correcting static errors, and is increasingly being used to compensate dynamic nonlinearities, including settling errors and harmonic distortion.

Taken together, innovations in these areas have advanced the state of the art in high speed data conversion substantially.

Making It Work

Implementing a broadband mixed-signal system takes more than just the right data converter—these systems can place stringent demands on other portions of the signal chain. Again, the challenge is to realize good dynamic range over a wide bandwidth—getting more signal into and out of the digital domain to take advantage of the processing power there.

  • Broadband signal conditioning—in conventional single carrier systems, signal conditioning is about removing unwanted signals as quickly as possible, and then amplifying the desired signals. This often involves selective filtering, and narrowband systems that are tuned to the signals of interest. These tuned circuits can be very effective in realizing gain, and, in some cases, frequency planning techniques can be used to ensure that harmonics or other spurs fall out of band. Broadband systems can’t use these narrowband techniques, and it can be quite challenging to realize broadband amplification in these systems.
  • Data interfaces—conventional CMOS interfaces can’t support data rates of much greater than 100 MHz—and low voltages differential swing (LVDS) data interfaces run up to 800 MHz to 1 GHz. For larger data rates, one can shift to multiple bus interfaces, or move to SERDES interfaces. Contemporary data converters are using SERDES interfaces at up to 12.5 GSPS (as specified in the JESD204B standard)—multiple data lanes can be used to support different combinations of resolution and speed in the converter interface. These interfaces can be quite sophisticated in their own right.
  • Clock interface—processing high speed signals can also be very demanding regarding the quality of the clock used in the system. Jitter/error in the time domain translates into noise or errors in the signal, as illustrated in figure 5. For processing signals at greater than 100 MHz, clock jitter or phase noise can become a limiting factor in the useable dynamic range of the converter. Digital quality clocks may be insufficient for these sorts of systems, and high performance clocks may be required.

Figure 5. How error in the clock becomes error in the signal


The trend to broader band signals and software-defined systems is accelerating, and the industry continues to come up with innovative new ways to build better, faster data converters, pushing the dimensions of bandwidth, dynamic range, and power efficiency to new benchmarks.


David H Robertson

David H. Robertson

David H. Robertson has been with the Data Converter group of Analog Devices since 1985. He has worked on a wide variety of high speed digital-to-analog and analog-to-digital converters on complementary bipolar, BiCMOS, and CMOS processes. He has held positions as a Product Engineer, Design Engineer, and Product Line Director, working with product development teams in the US, Ireland, Korea, Japan, and China. Dave is presently the Product and Technology Director for ADI’s High Speed Converter group. Dave holds 15 patents on converter and mixed-signal circuits, has participated in two “best panel” International Solid-State Circuits Conference evening panel sessions, and was coauthor of the paper that received the IEEE Journal of Solid-State Circuits 1997 Best Paper Award. He served on the ISSCC technical program committee from 2000 through 2008, chairing the Analog and Data Converter subcommittees from 2002 to 2008.