Distributed Read Examples for the LTC2512-24

This article provides additional examples to more thoroughly explain the distributed read capability used in the LTC2512-24 24-bit over-sampling ADC with configurable flat passband digital filter. The data sheet explains that the data can be read over multiple conversions, that it allows for a slower serial clock and that transfers should be avoided while an actual conversion occurs. There is also a figure that shows one bit being read for the first 24 conversions of a DF number of conversions. This combined with the information in the data sheet tables is adequate but additional figures may be beneficial to other configurations. The examples shown here will deal specifically with the LTC2512-24 but these same concepts can be applied to the LTC2508-32. All examples shown are waveforms captured from the DC2222A-C demo board for the LTC2512-24.

Figure 1 shows a 24-bit transfer with DF = 4. The first transfer group of six bits begins after the falling edge of DRL. No data is transferred from the time MCLK goes high until the conversion has finished, a minimum of 473ns later. The data is grouped into four six bit transfers. This allows the full 1.6Msps conversion rate to occur with a 400ksps data rate using a 62.4MHz SCKA frequency.

Figure 1. LTC2512-24 24-bit distributed read, DF=4

Figure 1. LTC2512-24 24-bit distributed read, DF = 4

A zoomed image showing only two of the six bit transfers is shown in Figure 2. Here it is possible to see the individual SCKA cycles. Also note the tquiet time between the last SCKA cycle of each group and the rising edge of each MCLK pulse. Clocking out 24-bits only provides the conversion data. By clocking out 32-bits in four groups of 8-bits it is possible to also provide the configuration word to verify that the desired DF value was used. This is shown in Figure 3. To transfer all 32-bits with DF = 4 at the maximum conversion rate requires an SCKA frequency of 70.4MHz. Using DF = 8 and doing eight four bit transfers, an SCKA frequency of 35.2MHz could be used.

Figure 2. Zoomed LTC2512-24 24-bit distributed read, DF=4

Figure 2. Zoomed LTC2512-24 24-bit distributed read, DF = 4

The additional information and examples presented here show how to expand upon the data sheet explanation for more complex configurations.

Figure 3. LTC2512-24 32-bit distributed read, DF=4

Figure 3. LTC2512-24 32-bit distributed read, DF = 4

Author

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Guy Hoover

Guy Hoover is an engineer with over 30 years of experience at Linear Technology as a technician, an IC design engineer and an applications engineer.

He began his career at LTC as a technician, learning from Bob Dobkin, Bob Widlar, Carl Nelson and Tom Redfern working on a variety of products including op amps, comparators, switching regulators and ADCs. He also spent considerable time during this period writing test programs for the characterization of these parts.

The next part of his career at LTC was spent learning PSpice and designing SAR ADCs. Products designed by Guy include the LTC1197 family of 10-bit ADCs and the LTC1864 family of 12-bit and 16-bit ADCs.

Guy is currently an applications engineer in the Mixed Signal group specializing in SAR ADC applications support. This includes designing, writing Verilog code and test procedures for SAR ADC demo boards, helping customers optimize their products that contain LTC SAR ADCs, and writing hopefully useful applications articles that pass on to customers what he has learned about using these parts.

Guy graduated from DeVry Institute of Technology (Now DeVry University) with a BS in electronics engineering technology.