Anti-Alias Filter for 24-bit ADC

For many ADC applications a simple RC filter at the buffer input will provide adequate anti-alias filtering. For applications that require a higher order filter an active filter is often used. The active component in that filter must have sufficient bandwidth, fast settling, low noise and low offset so that it doesn’t corrupt the signal before it gets to the ADC. The LTC6363 is a differential op amp optimized to drive low power SAR ADCs. The LTC6363 has 500MHz GBW, 780ns settling to 4ppm, 2.9nV/√Hz and a maximum offset voltage of 100µV.

Figure 1 shows a 30kHz 3rd order filter using the LTC6363 that has been optimized for use with the LTC2380-24 1.5Msps/2Msps low power SAR ADC with an integrated digital filter. The LTC2380-24 can average from 1 to 65536 conversion results in real time providing an increase in SNR. Both inputs of this circuit can be driven differentially with a ±2.5Vpp signal range or one input can be grounded with the other input driven with up to a ± 5Vpp signal.

Figure 1. 30 kHz 3rd order filter drives LTC2380-24 24-bit ADC

Figure 1. 30 kHz 3rd order filter drives LTC2380-24 24-bit ADC

Figure 2 shows the combined frequency response of the filter and ADC with a sample rate of 1.5Msps and number of averages (N) set to 1 and 8. Figure 3 is a PScope screen capture that shows an FFT, SNR and THD for the circuit of Figure 1 with N = 1. Figures 4 and 5 show THD and SNR vs input frequency for the circuit of Figure 1 with N equal to 1 and 8. At input frequencies below a few kilohertz performance is close to the typical data sheet numbers for SNR and THD. THD gracefully degrades as the input frequency increases beyond that.

Figure 2. Combined Frequency Response of Filter and ADC

Figure 2. Combined Frequency Response of Filter and ADC

Figure 3. PScope Screen Capture shows FFT, SNR and THD of Circuit of Figure 1 with N=1

Figure 3. PScope Screen Capture shows FFT, SNR and THD of Circuit of Figure 1 with N = 1

Figure 4. THD vs fin for the Circuit of Figure 1

Figure 4. THD vs fin for the Circuit of Figure 1

Figure 5. SNR vs fin for the Circuit of Figure 1

Figure 5. SNR vs fin for the Circuit of Figure 1

Author

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Guy Hoover

Guy Hoover is an engineer with over 30 years of experience at Linear Technology as a technician, an IC design engineer and an applications engineer.

He began his career at LTC as a technician, learning from Bob Dobkin, Bob Widlar, Carl Nelson and Tom Redfern working on a variety of products including op amps, comparators, switching regulators and ADCs. He also spent considerable time during this period writing test programs for the characterization of these parts.

The next part of his career at LTC was spent learning PSpice and designing SAR ADCs. Products designed by Guy include the LTC1197 family of 10-bit ADCs and the LTC1864 family of 12-bit and 16-bit ADCs.

Guy is currently an applications engineer in the Mixed Signal group specializing in SAR ADC applications support. This includes designing, writing Verilog code and test procedures for SAR ADC demo boards, helping customers optimize their products that contain LTC SAR ADCs, and writing hopefully useful applications articles that pass on to customers what he has learned about using these parts.

Guy graduated from DeVry Institute of Technology (Now DeVry University) with a BS in electronics engineering technology.