ALTERA STRATIX IV FPGA Interface for the LTC2000 2.5Gsps, 16-bit DAC with LVDS Inputs


This application note describes how to interface the LTC2000, 16-Bit, 2.5GSPS digital-to-analog converter (DAC) with high speed parallel low-voltage differential signaling (LVDS) inputs to an ALTERA® STRATIX® IV FPGA, taking advantage of the dedicated I/O functions of the FPGA family.

System hardware consists of a DC2085A LTC2000 evaluation board and a DK-DEV-4SGX230NSTRATIX IV GX Development Board. For more detailed information the DC2085 andSTRATIX IV GX FPGA Development Kits, refer to:

A simple software interface from a host PC is used to configure the hardware and load data patterns. DAC data patterns are stored in external double data rate type III synchronous dynamic random access memory (DDR3) with a maximum pattern depth of 256 megasamples, facilitating evaluation of very complex analog waveforms.

LTDACgen is a graphical program that generates sinusoidal and spread-spectrum patterns for evaluation the LTC2000 with this reference design. LinearLabTools allows direct control of this reference design from Matlab or Python, allowing customers to test with their own data patterns and incorporate other instruments into the evaluation process.

DAC LVDS Interface

The LTC2000’s digital interface consists of two 16-bit LVDS data streams, eachsupporting a data rate up to 1250 MSPS with a 625 MHz DDR clock.


Figure 1: LTC2000 Block Diagram

CK is the conversion clock that directly controls updates to the DAC output. The LTC2000 contains a programmable clock divider and LVDS transmitter which provide a divided version (either fCK/2 or fCK/4) of CK at the DCKO pins used by the host FPGA or ASIC.DCKI is the DDRdata clock input. The two 16- bits data busses clocked by DCKI are combined into a single 16-bit,double rate data stream by a MUX clocked by CK, which is then converted to an analog signal.Refer to the LTC2000 data sheet for more details.


Figure 2: LTC2000 Interface Timing Diagram

Table 1 summarizes the requirements for the clock generator and FPGA.

Signal name Speed Requirement (MAX) Source
CK 2.5GHz External Ultra Low Jitter/Noise Clock generator
Double Rate Data Stream 2.5GSPS Internal LTC2000

Demonstration System Architecture

The STRATIX IV GX FPGA development board provides a hardware platform for developing and prototyping low-power, high-performance and logic-intensive designs. The board contains a STRATIX IV GX FPGA EP4SGX230KF40 (BGA 1517 pins), 512Mbytes DDR3 SDRAM with a 64-bit data bus and 128Mbytes DDR3 SDRAM with a 16-bit data bus. It also provides a wide range of peripherals and interfaces to facilitate the development. Since the FPGA design is pretty simple for this application the device and board usage is very low.

The DC2085A board contains the LTC2000, power management circuitry allowing the use of a single 5V supply, and an FT2232H providing a USB interface for data transfer and control. The FT2232 is a USB 2.0 high speed (480Mbps) controller that can be configured for dual multi- protocol synchronous Serial Engine (MPSSE) mode or a single, high-speed synchronous FIFO mode. Channel B of the FT2232 in MPSSE mode implements a SPI interface for configuring the LTC2000.

The LTC2000 requires a low-jitter 2.5GHz (MAX) clock applied to the CK input. The DC2085A board is mated to the FPGA board by two High- Speed Mezzanine Card (HSMC) connectors. The connectors carry DCKO from the LTC2000, two 16- bits data streams (DA, DB) and the DCKI data capture clock generated by the FPGA. DCKO is used as the main FPGA clock, with the internal divider set to divide-by-4 for dual-port mode.  All high-speed signals are LVDS, using the TX side of the HSMC connectors.  Several of the HSMC RX signals are configured as CMOS GPIO, connected to the 8-bit FT2232 Synchronous FIFO port through which the host uploads the DAC pattern data.

The FPGA design also controls an LCD module included with the FPGA board. It displays buffer size configuration, FPGA status and current operation mode. The LCD circuit is on a dedicated clock domain, SYSCLK, which is from a 100MHz on board oscillator.

The FPGA bitfile is uploaded via an embedded “USB blaster” JTAG adapter. The bitfile can also be loaded into a configuration EEPROM that loads the FPGA on power-up.


Figure 3: Demonstration System Architecture

I/O Architecture of STRATIX IV FPGA

The STRATIX 4 GX device has built-in serializer/deserializer (SERDES) circuitry that supports high-speed LVDS interfaces at data rates of up to 1.6Gbps.  Pin assignment is important for STRATIX IV FPGA LVDS applications because only some of the I/O blocks support full LVDS features and only some of the PLLs support these I/Os. The STRATIX IV device family supports LVDS on both row and column I/O banks.

  • Column output buffers (located on the top and bottom sides) are single ended and need external termination schemes to support LVDS.
  • Row output buffers (located on the left and right sides) are true LVDS and only PLLs located on the left and right sides support these IOs.

Dedicated SERDES circuits are implemented on the row I/O banks to further enhance LVDS interface performance in the device. For column I/O banks, SERDES is implemented in the core logic because there is no dedicated SERDES circuitry on column I/O banks. Only true LVDS buffers and SERDES can be used in this application. The following dedicated components are contained in the SERDES circuitry:

  • Differential I/O buffer
  • Transmitter serializer
  • Receiver deserializer
  • Data realignment
  • DPA (Dynamic Phase Alignment)
  • Synchronizer (FIFO buffer)
  • Phase-locked loops (PLLs) (located on the left and right sides of the device)

The true differential I/O buffer’s direction is not configurable. The specific pin only supports one direction data flow.


Figure 4: STRATIX IV Differential Transmitter

This application only uses differential transmitters. Its dedicated circuitry consists of a differential buffer and a serializer. The clock source is from the left and right PLLs. The differential output buffer can drive out LVDS, mini-LVDS, and RSDS signaling levels. The serializer takes up to 10-bit wide parallel data from the FPGA fabric, clocks it into the load registers, and serializes it using shift registers clocked by the left and right PLL before sending the data to the differential buffer. The MSB of the parallel data is transmitted first.

Aserialization factor of ×3, ×4, ×6, ×7, ×8, or×10 and SDR and DDR modes can be set by the Quartus software.

The DDR3 memory that contains DAC data drives a slow, easily constrainable, 256-bit widedata bus.A FIFO handles clock domain crossing between the memory and LVDS transmitters. The transmitter block serializes the parallel data bus to 32 very high speed data streams as shown in Figure 5.  Since all serializers are clocked by one PLL, a very high speed 32-bit parallel data bus is generated. An additional serializer with a constant parallel input generates an adjustable DAC data input clock, DCKI, and is perfectly aligned with the data streams.


Figure 5: Differential Transmitter in LTC2000 FPGA Design

As Table 1 and Figure 5 illustrate, if output data streams are 1.25Gbps the parallel bus from the memory only needs 1.25G/8 = 156.25MHz clock. If using a 64-bit wide, 533MHz double data rate DDR3 module as DAC data storage the operating clock of output bus, 256-bit Avalon-MM bus, can drop speed down to 266.5MHhz. A simple FIFO circuit can convert the Avalon-MM bus to an identical width 156.25MHz parallel bus connected to the input ports of the differential transmitter.  Now the ultra high speed parts are only handled by FPGA dedicated SERDES blocks. The only critical timing issue is the 32-bits output data streams timing skew. Although there is no programmable delay element for true LVDS output buffer skew adjustment in the I/O block, STRATIX claims the channel-to-channel-skew (TCCS) is less than 100ps: The timing difference between the fastest and slowest output edges, including clock variation and clock skew, across channels driven by the same PLL. Total jitter (txjitter) for data rates from 600Mbps to 1.6Gbps is less then 160ps. So the data capture window for 1.25Gbps should be as shown in Figure 6 if we take care of PCB trace matching perfectly. Refer to for more detail.


Figure 6: Data Stream Capture Window

The STRATIX IV GX FPGA development board provides two DDR3 modules, 512-Mbyte DDR3 SDRAM with a 64-bit data bus located on the bottom port (Bank 3) and 128-Mbyte DDR3 SDRAM with a 16-bit data bus located on the top port (Bank 8). If using DDR3 on the top port, the 64-bit Avalon- MM bus doesn’t have enough bandwidth to expand to 256-bit/156.26MHz local parallel bus. So the 512-Mbyte DDR3 module is the only choice.


Figure 7: 512MB DDR3 Bottom Port Organization

The DDR3 bottom port consists of four DDR3 devices, Micron MT41J64M16LA-15E, providing a single 512-Mbyte interface with a 64-bit data bus. For detailed information on the particular Micron DDR3 SDRAM, refer to

This memory interface is designed to run between 300MHz, the minimum frequency for DDR3, and 533MHz for a maximum theoretical bandwidth of over 68.2GBps. The internal bus in the FPGA is typically 2 or 4 times the width at full-rate or half-rate respectively. For this application, a 533MHz 64-bit interface will become a 266.5MHz 256-bit bus.

ALTERA FPGAs achieve optimal DDR3 interface performance with a particular DDR3 interface IP. The IP provides the following components:

  • Physical layer interface (UniPHY) which builds the data path and manages timing transfers between the FPGA and the external DDR3 devices.
  • DDR3 controller (HPCII) which implements all the DDR3 commands and protocol-level requirements.

Figure 8: ALTERA DDR3 Controller and UniPHY IP Block Diagram

FT2232H Dual Channel USB Controller

The DC2085A board contains a FTDI dual channel USB controller, FT2232, to upload DAC data from the host and configure the LTC2000. FT2232 is set as synchronous FIFO mode to upload the data. The transfer rate is up to 25Mbytes/sec through an 8-bit wide bus with a few handshake signals. Only channel A can be configured as a FT245 style synchronous FIFO interface. When this mode is set the pins used and the descriptions of the signals are shown in Table 2.  In this mode channel B is not available since all resources have been switched onto channel A. The data is read on the rising edge of the CLKOUT.

Table 2: FT2232 Synchronous FIFO Interface Description

Signal Name Direction Synchronous FIFO Interface Description
ADBUS[7:0] Bi-direction D7 to D0 bidirectional FIFO data. This bus is configured as output in this application
RXF# Output When high, do not read data from the FIFO. When low, there is data available in the FIFO which can be read by driving RD# low. When in synchronous mode, data is transferred on every clock while both RXF# and RD# are low
RD# Input Enables the current FIFO data byte to be driven onto D0...D7 when RD# goes low. The next FIFO data byte (if available) is fetched from the receive FIFO buffer on each CLKOUT cycle until RD# goes high.
CLKOUT Output 60MHz Clock driven from the chip. All signals should be synchronized to this clock.

Figure 9: FT2232H Synchronous FIFO Interface Timing Diagram

Table 3: FT2232 Synchronous FIFO Interface Signal Timings

Name Minimum Typical Maximum Units Description
T1 16.67 ns CLKOUT period
T2 7.5 8.33 ns CLKOUT high period
T3 7.5 8.33 ns CLKOUT low period
T4 1 7.15 ns CLKOUT to RXF#
T5 1 7.15 ns CLKOUT to read DATA valid
T6 1 7.15 ns OE# to read DATA valid
T7 1 7.15 ns CLKOUT to OE#
T8 11 ns RD# setup time to CLKOUT (RD# low afterOE# low)
T9 0 ns RD# hold time

In order to configure the LTC2000 and FPGA, channel B of the FT2232 has to be set to multi-protocol synchronous serial Engine (MPSSE) mode. MPSSE can be independently configured to a number of industry standard serial interface protocols such as JTAG, I2C or SPI, or it can be used to implement a proprietary bus protocol. For this application it is set as SPI and GPIO interface and ports.

FPGA Design


Figure 10: FPGA Design Block Diagram

The following tables list the top level port descriptions.

Table 4: DDR3 interface

Signal Name Direction Description
pll_ref_clk Differential input DDR3 controller and UniFHY reference clock input
mem_a Output Row address
mem_ba Output Bank address
mem_ck Differential output The clock provided to external DDR3
mem_cke Output Clock enable
mem_cs_n Output Chip select
mem_ras_n Output Row address available
mem_cas_n Output column address available
mem_we_n Output Write enable
mem_dm Output DDR3 input data mask
mem_reset_n Output Reset DDR3
mem_dq Bi-direction Data bus
mem_dqs Differential Bi-direction Data strobe
mem_odt Output Enable DDR3 on chip termination
mem_rdp Input FPGA on chip termination input
mem_rdn Input FPGA on chip termination input

Table 5: System control interface

Signal Name Direction Description
SYSCLK Differential input System clock input
MPI2_RESET input Push button reset input
dacpd Output DAC power down control

Table 6: Configuration interface

Signal Name Direction Description
lcd_d_cn Output LCD data or command select
lcd_wen   Output LCD write enable
lcd_csn Output LCD chip select
lcd_data Bi-direction LCD data bus

Table 7: Configuration interface

Signal Name Direction Description
fifoclk Input FT2232 FIFO clock input. It will be connected to CLKOUT in Table 8 through HSMC
rxfn Input FIFO data available. It will be connected to RXF# in Table 8 through HSMC
rdn Output Read enable. It will be connected to RD# in Table 8 through HSMC
fifo_data_in Input DAC convert data input port. It will be connected to ADBUS[7:0] in table 8 through HSMC
actpls Input A pulse generated by FT2232 channel B GPIO. All below signals will be latched by the rising edge
hostrw Input Read/write select generated by FT2232 channel B GPIO
adflag Input Address/data select generated by FT2232 channel B GPIO
cfgrst Input Configuration reset input generated by FT2232 channel B GPIOs
adport Bi-direction 8-bit configuration data/address port implemented by FT2232 channel B GPIO

Table 8: LTC2000 Interface

Signal Name Direction Description
DDCK Differential input LTC2000 reference clock input
DCLK Differential output Data capture clock
DA1 Differential input 16-bit data stream
DA2 Differential input 16-bit data stream

The following table lists major clock domains in the design.

Table 9: FPGA Clock Tree

Clock source Frequency PLL Generated clock Loading Frequency of generated clock
DDCK 625MHz altpll_source1 fclk altlvds_tx1 1.25GHz
txclk altlvds_tx1 625MHz
othbclk m2f_ctrl, altfifo3 625MHz
SYSCLK 100MHz altpll_source0 sclk lcdrw_ctrl, lcdfl_ctrl 500kKHz
fifoclk 60MHz altpll_source2 othaclk f2m_ctrl, altfifo2 60MHz
pll_ref_clk 100MHz altpll_source1If0_pll0 afi_clk,
Mm_intererconnect, if0 266.5MHhz

The clocks from PLL altpll_source1 timing relationship is illustrated below:


Figure 11: PLL altpll_source1 Timing Diagram

DCKO from the LTC2000 DAC update clock divided by four, frequency rate up to 625MHz is feed into the PLL (altpll_source1) as the reference clock of the transmitter. The fclk and txclk are delivered to the differential transmitter (altlvds_tx1) to generate data streams DA1, DA2 and the DAC data input clock DCLK to the DAC. The txclk duty cycle and txclk, othbclk phases need to be adjusted to meet the timing requirement according to the FPGA post place and routing timing report. Current settings are: 13%, 101.25 degree, 101.25 degree. Different FPGA devices, implementation and even different board fabrication may require re-adjustment.


Figure 12: Function Simulation at 2.5Gsps


Figure 13: Post Place & Routing Simulation at 2.5Gsps


Figure 14: Post Place and Routing Simulation at 2.5Gsps Data Lines Skew

The DAC data is stored in an external 512Mbyte DDR3 SDRAM module on STRATIX FPGA board. The DDR3 memory controller design is based on ALTERA IP, DDR3 SDRAM controller with UniPHY v13.1. The IP consists of High Performance Controller II (HPCII) and UniPHY, a physical layer of the external memory interface. HPC II provides high memory bandwidth, high clock rate performance, and run-time programmability.  The controller can reorder data to reduce row conflicts and bus turn-around time by grouping reading and writing together, allowing for efficient traffic patterns and reduced latency. The IP is generated by the ALTERA tool, Megawizard Manager. The ALTERA Avalon-MM traffic processor has to be removed from the IP. For more detailed information regarding the DDR3 SDRAM controller with UniPHY and the IP generation flow, refer to memory-interface.jsp.

A special interface has been built to connect the FT2232 through HSMC to upload DAC data from the host PC. FT2232 must be set as synchronous FIFO mode before the data transfer. The pins connection relationship between the FPGA and FT2232 in DC2085A board is shown in Figure 15.


Figure 15: FT2232 section of DC 2085A board

The Write procedure is triggered by rxfn and driven by the FT2232.  When low it indicates that the DAC data is available in the FIFO of FT2232. FPGA responds to it by driving rdn low to captured the data from the internal FIFO of FT2232 to altfifo2, an 8-bit x 512 FIFO of the FPGA, through the 8-bit port fifo_data_in.  This FIFO expends the data bus to 256-bit wide and writes to DDR3 controller module mm_interconnect. The mm_interconnect issues the command to initialize the external DDR3 SDRAM, convert data to 128-bit format and send the data to external DDR3 memory through UniPYH if0.  The writing flow, shown in Figure 16, is totally controlled by circuit f2m_ctrol.  When all data is stored in the memory f2m_ctrl submits a command to the circuit m2f_ctrl to enable reading flow. The data is read from DDR3 through FHY as well as mm_interconnect. A circuit is built for interfacing the Avalon bus to a 256-bit x 4096 FIFO altfifo3. The FIFO altfifo3 buffers data from a 266.5MHz burst transfer bus to a 156.26MHz non-interrupted transfer bus as shown in Figure 17 . The FIFO output ports directly drive differential transmitter altlvds_tx1. The differential transmitter generates two data streams with 1.6Gsps bandwidth, 16-bit LVDS SERDES circuits and transmits to the LTC2000 through HSMC connectors as shown in Figure 10. The read flow is completely controlled by circuit m2f_ctrol. The efficiency of the DDR3 controller impacts the 266.5MHz bus operation. Lower efficiency will corrupt 156.26MHz non-interrupted bus, requiring the use of a larger FIFO. The two main factors that affect the efficiency are the interface standard specified by the memory vendor, and the way that you transfer data.


Figure 16: Data captured by altfifo2 is written to DDR3


Figure 17: Figure 17: Data read from DDR3 is transferred to the LTC2000 through altfifo3 and LVDS SERDES

f2m_ctrl and m2f_ctrl are configured by FTDI configuration which is accessed by FTDI channel B as shown in Figure 15. 12-bit GPIOs build a register map access bus following the protocol below:


Figure 18: FT2232 configuration port protocol

The following tables list the overall FPGA register mapping:

Table 10: FPGA ID Register

Bit 7 6 5 4 3 2 1 0
Bit Name ID
Read/Write Read/Write
Initial Value 0x1a

Table 11: FPGA Control Register

Bit 7 6 5 4 3 2 1 0
Read/Write Read/Write
Initial Value 0x00
  • RSV: Reserve
  • MODE: 1: One frame, only send out buffer data until end of buffer 0: Loopback, keep sending buffer data from beginning to end of buffer continuously until clock stops
  • MEMSIZE: Buffer size select

Table 12: Buffer Size Configuration

MEMSIZE Buffer Size
0 16K Samples
1 32K Samples
2 64K Samples
3 128K Samples
4 256K Samples
5 512K Samples
6 1M Samples
7 2M Samples
8 4M Samples
9 8M Samples
10 16M Samples
11 32M Samples
12 64M Samples
13 128M Samples
14 256M Samples
  • Unknown value will be recognized as 16K setting

Table 13: FPGA Status Register

Bit 7 6 5 4 3 2 1 0
Read/Write Read
Initial Value 0x00
  • FWRFUL: The FIFO writing data to external DDR3 is full.
  • FRDFUL: The FIFO reading data from external DDR3 is full.
  • DDRPLL: The embedded PLL of the DDR controller is locked.
  • DDRRDY: External DDR is ready to access.
  • PLL0: The PLL accepting SYSCLK is locked.
  • PLL1: The PLL accepting DDCK is locked.
  • PLL2: The PLL accepting fifoclk is locked.

Table 14: DAC Power Down Register

Bit 7 6 5 4 3 2 1 0
Read/Write Write
Initial Value 0x00
  • RSV: Reserve
  • DACPD: 1: Turn on DAC
                 0: Turn off DAC

The FPGA design implements a full function LCD driver for FPGA configuration and status display. It supports the Lumex LCD module SML- LX1206GC-TR attached to the STRATIX IV GX FPGA development board.

The LCD driver circuits lcdrw_ctrl, lcdfl_ctrl are clocked by a dedicated clock domain SYSCLK from the FPGA’s on board 100MHz oscillator. Shown below is the two rows 32 characters LCD display:

Figure 19: LCD Display

F P G A : X X X M O D E : Y Y
B U F S I Z E : Z Z Z Z S P s

Table 15: LCD DisplayInformation

Characters Display Description
FST Configuration reset
BST Push button reset
IF0 DDR3 controller not ready
CFG During configuration
CLK No LTC2000 clock input
RUN During normal operation
MF Loop back mode
SF One frame mode
ZZZZ (Samples count) See table3 Buffer Size

Reference Design

Table 16: Reference Design Matrix

Parameter Description
Developer Name Gary Yu
Source Code Provided Yes
Source Code Format Yes
Design Uses Code or IP from Existing Reference Design, Application Note, 3rd party, or Megawizard™ Software Yes
Functional Simulation Performed Yes
Timing Simulation Performed Yes
Testbench Provided for Functional and Timing Simulations Yes
Testbench Format Verilog
Simulator Software and Version NCVerilog (64bit) 08.20-s014
SPICE/IBIS Simulations No
Synthesis Software Tools and Version Quartus II v13.1.0
Implementation Software Tools and Version Quartus II v13.1.0
Static Timing Analysis Performed Yes
Hardware Verification
Hardware Verified Yes
Hardware Platform Used for Verification Linear Tech DC2085A board and STRATIX IV GX FPGA Development Board

The whole design, simulation and implementation environment are presented on the redhat LINUX operating system. The directories are set up as shown in Figure 20.

Figure 20: Design and simulation files folder_a

Figure 20: Design and simulation files folder

System Configuration Flow

  • Turn on LTC2000 update clock source.
  • Turn on FPGA board power (system clock shouldbe present).
  • Turn on FPGA board power (system clock shouldbe present).
  • Turn on DC2085A board power.
  • Load FPGA image.
  • Configure FTDI as MPSSE mode.
  • Generate a reset pulse to FPGA on GPIOL3/BDBUS7 of FTDI.
  • Check FPGA ID register by FTDI configuration port to verify FPGA image is correct.
  • Set FPGA Control Register bits MEMSIZE and MODE to configure buffer size and transfer mode.
  • Turn on LTC2000 by setting DAC power down register bit DACPD.
  • Configure LTC2000 through SPI by FTDI.
  • Check FPGA Clock status register bit DDRRDY, PLL0, PLL1, DDRPLL by FTDI configuration port to verify system clock; check that the DDR3 controller reference clock and DDCK from the STRATIX FPGA boardand LTC2000 are available. DDR3 initialization is done.
  • Configure FTDI as FIFO mode.
  • Start to send DAC data to FPGA through FTDI.
  • Monitor LCD display and waveform from LTC2000 output.


The Altera Stratix 4 GX FPGA family has a number of useful features that allow the design of a robust interface to the LTC2000. The design presented in this application note can be used directly as an evaluation tool for the DAC. The high-speed data interface may be used as a starting point for customer designs.

An Altera Quartus Archive of this project is available at The LTDACgen software interfaces with this reference design, and allows users to easily program sinusoidal and spread spectrum patterns for evaluation of the LTC2000. LTDACgen is available at LinearLabTools allows direct control of this reference design from Matlab or Python, allowing customers to test the LTC2000 with their own data patterns and incorporate other instruments into the evaluation process. LinearLabTools is available at



Gary Yu