Clock Generator PLL with Integrated VCO
An additional divider stage allows division of the VCO signal. The CMOS level output is equivalent to the VCO signal divided by integer value between 2 and 31. This divided signal can be further divided by two if desired.
Control of all the on-chip registers is through a simple 3-wire interface. The device operates with a power supply ranging from 3.0 V to 3.6 V and can be powered down when not in use.
Data Sheet, Rev. A, 3/08
At least one model within this product family is in production and available for purchase. The product is appropriate for new designs but newer alternatives may exist.
This page contains ordering information for the evaluation board used to evaluate the ADF4360-9 Clock Generator PLL with Integrated VCO.
Recommended Linear Regulators
Recommended Divide-by-4 Prescaler
- For a low noise, low power, fixed RF block: ADF5001.
Recommended PLL Active Filter
- For an ultralow noise, rail-to-rail amplifier: OP184.
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