Dual, Integer-N 1.1 GHz / 2.0 GHz PLL
The ADF420x family of dual frequency synthesizers are used to implement local oscillators in the upconversion and downconversion sections of wireless receivers and transmitters. Each synthesizer consists of a low noise, digital, phase frequency detector (PFD); a precision charge pump; a programmable reference divider; programmable A and B counters; and a dual modulus prescaler (P/P + 1). The A (6-bit) and B (11-bit) counters, in conjunction with the dual modulus prescaler (P/P + 1), implement an N divider (N = BP + A). In addition, the 14-bit reference counter (R counter) allows selectable REFIN frequencies at the PFD input. The on-chip oscillator circuitry allows the reference input to be derived from crystal oscillators.
A complete phase-locked loop (PLL) can be implemented if the synthesizers are used with an external loop filter and voltage controlled oscillators (VCOs).
Control of all the on-chip registers is via a simple 3-wire interface. The devices operate with a power supply ranging from 2.7 V to 5.5 V and can be powered down when not in use.
- Wireless handsets (GSM, PCS, DCS, CDMA, WCDMA)
- Base stations for wireless radio (GSM, PCS, DCS, CDMA, WCDMA)
- Wireless LANS Communications test equipment
- CATV equipment
At least one model within this product family is in production and available for purchase. The product is appropriate for new designs but newer alternatives may exist.
Recommended Linear Regulators
Recommended Divide-by-4 Prescaler
- For a low noise, low power, fixed RF block , we recommend the ADF5001 .
Recommended PLL Active Filter
- For an ultralow noise, rail-to-rail amplifier , we recommend the OP184 .
Phase Locked Loops for High-Frequency Receivers and Transmitters – Part 1
Phase-Locked Loops for High-Frequency Receivers and Transmitters - Part 2
Phase Locked Loops for High-Frequency Receivers and Transmitters – Part 3
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