7 GHz integer-N PLL
The ADF4107 frequency synthesizer can be used to implement local oscillators in the up-conversion and down-conversion sections of wireless receivers and transmitters. It consists of a low-noise digital PFD (phase frequency detector), a precision charge pump, a programmable reference divider, programmable A and B counters, and a dual-modulus prescaler (P/P + 1). The A (6-bit) and B (13-bit) counters, in conjunction with the dual-modulus prescaler (P/P + 1), implement an N divider (N = BP + A). In addition, the 14-bit reference counter (R counter), allows selectable REFIN frequencies at the PFD input. A complete PLL (phase-locked loop) can be implemented if the synthesizer is used with an external loop filter and VCO (voltage controlled oscillator). Its very high bandwidth means that frequency doublers can be eliminated in many high frequency systems, simplifying system architecture and reducing cost.
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At least one model within this product family is in production and available for purchase. The product is appropriate for new designs but newer alternatives may exist.
This evaluation board requires an SDP Controller board for connection to the PC. The SDP controller board connects to the PC via USB 2.0. The evaluation board will connect to the SDP controller board. The evaluation board cannot be connected directly to the PC. The evaluation software running on the PC will communicate through the SDP Controller board, to the evaluation board. The SDP Controller board is a separate list item in the ordering guide below (EVAL-SDP-CS1Z). If you have not previously purchased an SDP Controller board, please do so to ensure a full evaluation setup.
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