The ADF4001 frequency synthesizer can be used to implement clock sources for PLLs that require very low noise, stable reference signals. It consists of a low-noise digital PFD (Phase Frequency Detector), a precision charge pump, a programmable reference divider, and a programmable 13-bit N counter. In addition, the 14-bit reference counter (R Counter), allows selectable REFIN frequencies at the PFD input. A complete PLL (Phase-Locked Loop) can be implemented if the synthesizer is used with an external loop filter and VCO (Voltage Controlled Oscillator) or VCXO (Voltage Controlled Crystal Oscillator). The N min value of 1 allows flexibility in clock generation.
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This page contains ordering information for the evaluation board used to evaluate the ADF4001 200 MHz Clock Generator PLL.
This evaluation board requires an SDP Controller board for connection to the PC. The SDP controller board connects to the PC via USB 2.0. The evaluation board will connect to the SDP controller board. The evaluation board cannot be connected directly to the PC. The evaluation software running on the PC will communicate through the SDP Controller board, to the evaluation board. The SDP Controller board is a separate list item in the ordering guide below (EVAL-SDP-CS1Z). If you have not previously purchased an SDP Controller board, please do so to ensure a full evaluation setup.
Recommended Linear Regulators
Recommended Divide-by-4 Prescaler
- For a low noise, low power, fixed RF block , we recommend the ADF5001 .
Recommended PLL Active Filter
- For an ultralow noise, rail-to-rail amplifier , we recommend the OP184 .
Ask the Applications Engineer—30: PLL SYNTHESIZERS
(Analog Dialogue, Vol. 36, No. 3, May-July, 2002)
Phase Locked Loops for High-Frequency Receivers and Transmitters – Part 1
Phase-Locked Loops for High-Frequency Receivers and Transmitters - Part 2
Phase Locked Loops for High-Frequency Receivers and Transmitters – Part 3