DC to 2.0 GHz Multiplier
The ADL5391 draws on three decades of experience in advanced analog multiplier products. It provides the same general mathematical function that has been field proven to provide an exceptional degree of versatility in function synthesis:
VW = α × (VX x VY)/1 V + VZ
The most significant advance in the ADL5391 is the use of a new multiplier core architecture, which differs markedly from the conventional form that has been in use since 1970. The conventional structure that employs a current mode, translinear core, is fundamentally asymmetric with respect to the X and Y inputs, leading to relative amplitude and timing misalignments that are problematic at high frequencies. The new multiplier core eliminates these misalignments by offering symmetric signal paths for both X and Y inputs. The Z input allows a signal to be added directly to the output. This can be used to cancel a carrier or to apply a static offset voltage.
The ADL5391 is fabricated on Analog Devices' proprietary, high performance, 65 GHz, SOI complementary SiGe bipolar IC process. It is available in a 16-lead, Pb-free, LFCSP and operates over a -40°C to +85°C temperature range. Evaluation boards are available.
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At least one model within this product family is in production and available for purchase. The product is appropriate for new designs but newer alternatives may exist.
The ADL5391-EVALZ is a fully populated, 4-layer, FR4-based evaluation board designed to allow easy evaluation of all features of the ADL5391. Signal inputs and signal output SMA connections with single ended setups are featured. There is an option of full differential signaling on all signal inputs and output at card edge. Access to the +5 V/135 mA supply is achieved with clip leads to the VPOS and COMM testpoints; it has a range from +4.5 to +5.5 V.