Documentation Errata for SHARC® Processor Programming Reference (Includes ADSP-2136x, ADSP-2137x, and ADSP-214xx Processors)

Chapter: 3 / Page 35

Doc ID: DOC-1431

Change

The following information is missing from the constraints on programming multifunction instructions:

For any instruction with multiple operations executing in parallel, the destination registers should not be the same.

Chapter: 3 / Page 214

Doc ID: DOC-1414

Change

Because bit FIFO operations (BITDEP and BITEXT) do not work as expected in SIMD mode, the following note must be added:

Note: SIMD must be disabled during bit FIFO operations.

This information should appear immediately after:

  • Table 3-9 on page 3-32
  • Table 4-39 on page 4-96

Chapter: 4 / Page 13

Doc ID: DOC-1742

Change

Under the PC Stack Manipulation section, the statement "For example a write to PCSTKP = 3 deletes all entries except the three oldest. " is incorrect. The PCSTKP = 3 instruction does not delete the PCSTK entries. The quoted statement must be removed.

Chapter: 4 / Page 67

Doc ID: DOC-1585

Change

Before the bullet list in the Nested Loops section the two sentences need to change from:

If using counter based instructions the following occurs:

Within the loop sequencer, two separate loop counters operate:

And, need to change to:

If using counter based instructions, within the loop sequencer, two separate loop counters operate:

Chapter: 4 / Page 92

Doc ID: DOC-1453

Change

Table 4-37 requires modification because the behavior of floating-point comparisons deviates slightly from the IEEE 754 specification. The required changes are as follows:

Current Description Modified Description
ALU > 0 ALU > 0 or unordered 7
ALU ≥ 0 ALU ≥ 0 or unordered 7

7 The unordered condition arises from floating-point instructions in which an operand is NaN (Not a Number). Note that by the inclusion of this case, the GT and GE conditions (GT and GE) differ from the IEEE 754 definitions.

Chapter: 4 / Page 194

Doc ID: DOC-1463

Change

Some of the information for the loop restoration stack in unclear. The following changes are required on page 4-76:

Current Wording Correct Wording
However, popping and pushing the loop and PC stack to temporarily vacate the stacks can still be performed such that this information is recreated automatically by following the procedure described in the next section. However, popping and pushing the loop and PC stack to temporarily vacate the stacks can still be performed from an ISR by following the procedure described in the next section.
Popping and Pushing Loop and PC Stack Inside an Active Loop Popping and Pushing Loop and PC Stacks From an ISR
Use the following sequence to pop and push LADDR/CURLCNTR and PCSTK inside an active loop to temporarily vacate the stacks. Use the following sequence to pop and push LADDR/CURLCNTR and PCSTK to temporarily vacate the stacks.
Sequence a-b-c is critical and therefore must be followed strictly. Any number of unrelated instructions may be executed between the a-b-c sequence. Sequence a-b-c is critical and therefore must be followed strictly. Any number of unrelated instructions may be executed between the a-b-c sequence.
Note: Interrupts should not be triggered during sequence a-b-c. This can be achieved by clearing the IRPTEN bit in the MODE1 register. Consider the two cycles of effect latency before the restoration sequence starting with instruction 'a' and then set the IRPTEN bit after instruction 'c', after the restoration is complete.

Chapter: 9 / Page 16

Doc ID: DOC-1433

Change

The following information is missing from the constraints on programming multifunction instructions on page 9-16 and page 9-24:

For any instruction with multiple operations executing in parallel, the destination registers should not be the same.

In addition:

  • The following example is missing from page 9-16:

    R5 , R1 = dm ( I0,M0 ) (LW); // In this case R0 is the long word pair for R1

    This instruction is invalid because both operations are updating R0 simultaneously.

  • The following example is missing from page 9-24:

    If EQ R0 = R4 + R5, S0 = R3; // With SIMD enabled

    This instruction is invalid because R0 is updated in the first operation if the condition is true in PEx, and in the second operation because SIMD is enabled.

Chapter: 11 / Page 37

Doc ID: DOC-1426

Change

The following information is missing from the description of the TRUNC instruction:

Note: For the instruction Rn = TRUNC Fx by Ry, when the scaling factor Ry < -256, the result is -1 instead of 0. This behavior deviates from IEEE standards.


Last Update Date: Oct 17 2017

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