104 MSPS, Four-Channel Digital Transmit Signal Processor (TSP)
The AD6623 is pin compatible to the AD6622 and can operate in AD6622 compatible control register mode.
Each TSP has five cascaded signal processing elements: a programmable interpolating RAM Coefficient Filter (RCF), a programmable Scale and Power Ramp, a programmable 5th order Cascaded Integrator Comb (CIC5) interpolating filter, a flexible 2nd order Re-Sampling Cascaded Integrator Comb filter (rCIC2), and a Numerically Controlled Oscillator/tuner (NCO). The AD6623 has four identical digital TSPs complete with synchronization circuitry and cascadable wideband channel summation. The outputs of the four TSPs are summed and scaled on-chip. In multi-carrier channel wideband transmitters, a bi-directional bus allows the Parallel (wideband) IF Input/Output to drive a second DAC. In this operational mode two AD6623 channels drive one DAC and the other two AD6623 channels drive a second DAC. Multiple AD6623s may be combined by driving the INOUT[17:0] of the succeeding with the OUT[17:0] of the preceding chip. The INOUT[17:0] can alternatively be masked off by software to allow preceding AD6623s outputs to be ignored.
Each channel accepts input data from independent serial ports that may be connected directly to the serial port of Digital Signal Processor (DSP) chips. The AD6623 utilizes a 3.3V I/O power supply and a 2.5V core power supply. All I/O pins are 5V tolerant. All control registers and coefficient values are programmed through a generic microprocessor interface. Intel and Motorola microprocessor bus modes are supported. All inputs and outputs are LVCMOS compatible.
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